State Machine Engine Parallel Pattern Recognition
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Solution Overview
Problem
Conventional computing systems face inefficiencies in pattern recognition due to the increasing volume of data and number of patterns to be identified, leading to bottlenecks in processing and reduced throughput, as they often require sequential search methods across multiple circuits, which can slow data receipt and increase scheduling inefficiencies.
Innovation Solution
A state machine engine employing finite state machine lattices arranged in a hierarchical parallel configuration, allowing multiple FSMs to analyze the same data in parallel, with outputs from lower-level lattices serving as inputs to higher-level ones, enabling rapid analysis of complex patterns across high-speed data streams without slowing down the data stream.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sequential search methods are used across multiple circuits, then pattern recognition can be performed, but processing speed decreases and throughput is reduced
Solution Approach 1:
The patent divides the pattern recognition task into multiple segments, with each circuit responsible for detecting specific patterns in parallel. This segmentation allows simultaneous processing of multiple patterns across different circuits, eliminating the sequential bottleneck while maintaining detection accuracy for each pattern type.
Solution Approach 2:
The patent combines multiple pattern detection circuits into a unified parallel processing architecture where all circuits operate simultaneously on the same data stream. This merging of parallel circuits increases overall throughput while each individual circuit maintains its pattern recognition capability.
2Productivity
If a large number of circuits operate in parallel to search data streams, then processing speed increases, but intermediate results become larger than original input data causing scheduling inefficiency
Solution Approach 1:
The patent extracts only the essential pattern match results from each parallel circuit rather than processing and transmitting all intermediate data. By taking out only the relevant detection outcomes, the system maintains high processing speed while minimizing intermediate data volume and associated scheduling complexity.
Solution Approach 2:
The patent transitions from processing data in a single dimension (sequential circuit operations) to multiple dimensions by implementing hierarchical parallel processing. This dimensional change allows the system to handle complex patterns through multi-layered parallel circuits while organizing intermediate results in a structured manner that reduces overall data volume.
3Adaptability or versatility
If the number of patterns to be identified increases, then pattern recognition capability improves, but the delay before the system is ready to search the next portion of data stream increases
Solution Approach 1:
The patent implements preliminary action by pre-configuring multiple parallel circuits with different pattern detection capabilities before data processing begins. This allows the system to immediately start searching for multiple patterns simultaneously without sequential setup delays, as all detection mechanisms are ready in advance.
Solution Approach 2:
The patent ensures continuity of useful action by maintaining all parallel pattern detection circuits in an active state throughout data processing. Unlike sequential methods that idle between pattern searches, this continuous parallel operation eliminates preparation delays and maintains constant productivity regardless of the number of patterns being detected.
Data Source
AI summary
In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.