Table-Based State Machine Pipelining for Parallel State Lookup
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Solution Overview
Problem
Table-based state machines face performance limitations due to sequential processing and slow memory access, which hinder parallelization and high clock frequency operations.
Innovation Solution
The implementation of a high-performance table-based state machine that reduces dependence on the current state by using a state table circuit to read all possible current states and an output multiplexer to select the next state and output, allowing pipelining of state table reads and enabling parallel processing of multiple inputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If table lookup is used for each iteration in a state machine, then the state transition accuracy is improved, but the processing speed deteriorates due to sequential memory access
Solution Approach 1:
The patent segments the state machine processing into parallel pipelines, where each pipeline processes a different input simultaneously. The state table is divided into multiple banks that can be accessed in parallel, eliminating the sequential bottleneck while maintaining accurate state transitions through dedicated lookup paths for each pipeline.
Solution Approach 2:
The patent transitions from sequential single-input processing to parallel multi-input processing by adding a temporal dimension. Multiple inputs are processed simultaneously across different pipeline stages, with each stage performing table lookups for its assigned inputs without waiting for previous inputs to complete, thereby increasing throughput while maintaining accuracy.
2Device complexity
If sequential processing is used for state machine iterations, then the implementation complexity is reduced, but the productivity deteriorates due to inability to parallelize
Solution Approach 1:
The state machine is segmented into multiple independent processing pipelines that operate in parallel. Each pipeline handles a subset of inputs with its own state table access logic, allowing throughput to scale with the number of pipelines while keeping individual pipeline complexity manageable and similar to traditional sequential designs.
Solution Approach 2:
Multiple sequential processing units are merged into a single parallel processing system where inputs are distributed across pipelines. The output of each pipeline is combined to form the complete result set, achieving high throughput while maintaining implementation simplicity through modular pipeline design that can be instantiated multiple times.
3Productivity
If all possible current states are read from state table circuit for each input, then the parallel processing capability is improved, but the memory access complexity increases
Solution Approach 1:
Each processing pipeline is assigned a specific subset of inputs and corresponds to particular state table banks. The memory access pattern is optimized locally for each pipeline, with each pipeline accessing only the state table entries relevant to its assigned inputs and current states, reducing overall memory access complexity while enabling parallel processing of multiple inputs simultaneously.
Data Source
AI summary
A table-based state machine is improved by reducing critical dependence path. In one aspect, all current states for a given input are read from a state table circuit, and the next state and output are then selected therefrom by an output multiplexer based on the current state, removing dependence on the current state from the table read, and allowing the read(s) to be pipelined. In a further aspect, multiple input units are configured to operate on multiple inputs in parallel, with each input unit propagating its state table circuit for its current input to the next downstream input unit. Each downstream input unit is configured to use the propagated state table circuit to provide the state table circuit reads to the proper output multiplexer input. The number of possible output states for a given input may be dynamically reduced, reducing the size of the output multiplexer selecting the next state.