Pseudo-Random State Machine Feedback for Fast Word Generation
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Solution Overview
Problem
Existing pseudo-random number generators, particularly pseudo-random number generators, face challenges in generating high-speed pseudo-random word streams with sufficient statistical randomness, which is crucial for applications like numerical simulations and cryptographic processes, due to their deterministic nature and limitations in operational speed.
Innovation Solution
A state machine with clocked registers and a feedback circuit that utilizes a logic stage and adder with XOR or XNOR gates to generate pseudo-random word streams by selectively weighing register output signals based on multi-transmission matrix elements, enabling faster generation of pseudo-random bit sequences and word streams with improved statistical distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pseudo-random number generators are used to generate high-speed pseudo-random word streams, then generation speed increases, but statistical randomness deteriorates due to deterministic nature
Solution Approach 1:
The patent segments the pseudo-random number generation process into multiple independent linear feedback shift registers (LFSRs), each generating a separate bit stream. By combining multiple segmented streams through XOR operations, the system achieves both high generation speed (parallel operation) and improved statistical randomness (diversity of sources), resolving the contradiction between speed and reliability
Solution Approach 2:
The patent creates a composite pseudo-random stream by combining multiple individual LFSR outputs. Each LFSR acts as a component with different statistical properties, and their combination through XOR operations produces a composite stream with superior statistical characteristics while maintaining high generation speed, effectively resolving the contradiction
2Productivity
If pseudo-random number generators operate at higher operational speeds, then processing efficiency improves, but implementation complexity increases
Solution Approach 1:
The patent divides the high-speed generation task into multiple parallel LFSR segments, each operating at manageable speeds. This segmentation allows the system to achieve high overall productivity through parallel processing while keeping each individual component's implementation complexity low and manageable
Solution Approach 2:
The patent replaces complex sequential generation mechanisms with simpler parallel LFSR structures combined with XOR logic. This substitution enables high processing efficiency through parallel operation while reducing implementation complexity by using standard, well-understood digital logic components
Data Source
AI summary
An embodiment of a state machine for generating a pseudo-random word stream, each word of the word stream including a plurality of subsequent bits of a pseudo-random bit sequence includes a plurality of clock registers and a feedback circuit coupled to the registers and adapted to provide a plurality of feedback signals to the registers based on a feedback function and a plurality of register output signals of the registers, wherein the state machine is configured such that a first word defined by the plurality of register output signals includes a first set of subsequent bits of a pseudo-random bit stream and such that a subsequent second word defined by the plurality of register output signals includes a second set of subsequent bits of a pseudo-random bit stream.