State Recovery Mechanism for Optimized Code Execution

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Solution Overview

Problem

Computing platforms face challenges in recovering the state of registers and pointers when transitioning from optimized to original code, particularly after events like interrupts or exceptions, due to differences in instructions and order between the two.

Innovation Solution

The implementation of a state recovery mechanism that inserts instructions and metadata into translated code to track and recover register and pointer values using bitvectors, avoiding repeated data movement and overhead, by utilizing vector widening optimization and restricted transactional memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If code optimization techniques are applied to translate original code into optimized code, then execution performance is improved, but state recovery complexity increases when interrupts or exceptions occur

Engineering Contradiction:
Improveexecution performanceVSAvoidstate recovery complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-saving the program counter (PC) value to a recovery register before executing optimized code. This allows the system to quickly restore the original code execution state when an interrupt or exception occurs, without needing to perform complex analysis of the optimized code structure during the recovery process. The PC value is saved in advance at known checkpoints in the optimized code, enabling rapid state recovery.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If translated code uses different instructions and different instruction ordering than original code, then resource utilization is optimized, but state recovery accuracy deteriorates

Engineering Contradiction:
Improveresource utilizationVSAvoidstate recovery accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent introduces a recovery register as an intermediary component that stores the program counter value. This intermediary allows the system to bridge the gap between the optimized code execution path and the original code execution path. When an interrupt occurs, the recovery register provides the correct PC value that corresponds to the original code location, ensuring accurate state recovery despite the differences in instruction sequence between original and optimized code.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If state recovery mechanisms are implemented for optimized code, then system reliability is improved, but execution overhead increases

Engineering Contradiction:
Improvestate recovery capabilityVSAvoidexecution overhead
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts only the essential state information (program counter value) that needs to be recovered, rather than saving and restoring entire register files or memory states. By extracting just the critical PC value to a dedicated recovery register, the system achieves reliable state recovery with minimal overhead, avoiding the time-consuming process of saving and restoring complete processor states.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS10635418B2State recovery methods and apparatus for computing platforms
Publication Date: 2020.04.28 INTEL CORP
  • US10635418B2 patent drawing
  • US10635418B2 patent drawing
  • US10635418B2 patent drawing

AI summary

State recovery methods and apparatus for computing platforms are disclosed. An example method includes inserting, with a processor, a first instruction into optimized code to cause a first portion of a register in a first state to be saved to memory before execution of a region of the optimized code, maintaining, with the processor, a first indication of a first manner in which the first portion of the register is to be restored in connection with a state recovery after execution of the region of the optimized code, and maintaining, with the processor, a second indication of a second manner in which a second portion of the register is to be restored in connection with the state recovery after execution of the region of the optimized code.