State Retention Latch Circuit for Low-Leakage Power Reduction
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Solution Overview
Problem
Conventional state retention circuits in power reduction modes consume significant power due to always-on buffers, which are necessary to maintain the state of data storage elements across a large semiconductor die, leading to substantial leakage current and power consumption.
Innovation Solution
A state retention circuit that includes a storage latch powered by a retention supply voltage, with a retention latch comprising a retention transistor and inverter, which toggles the retention node to store the state during normal mode and maintains it at a stable voltage during power reduction mode, allowing the buffer tree to be powered down, reducing overall power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an always on buffer (AOB) tree is used to route retention signals to storage latches during power reduction mode, then the state of data storage elements is reliably retained, but a considerable amount of leakage current flows to maintain power to each AOB, consuming significant power
Solution Approach 1:
The patent transitions the buffer tree from an always-on static state to a dynamic state by powering it down during power reduction mode. The buffer tree is controlled by a power mode control circuit that enables it during normal mode and disables it during power reduction mode, allowing the system to adapt its power consumption based on operational requirements while maintaining state retention functionality when needed.
Solution Approach 2:
The patent implements periodic toggling of the retention node state (between first and second states) to save the state of data storage elements before entering power reduction mode. This periodic action ensures that state information is captured at appropriate intervals without requiring continuous buffering, thereby reducing power consumption during idle periods.
2Use of energy by moving object
If the buffer tree is powered down during power reduction mode to reduce power consumption, then leakage current is minimized, but the retention signal cannot be reliably delivered to storage latches
Solution Approach 1:
The patent performs preliminary toggling of the retention node state before entering power reduction mode to save the state of data storage elements. This preliminary action ensures that all necessary state information is captured and stored in storage latches before the buffer tree is powered down, eliminating the need for continuous buffering while maintaining reliability.
Solution Approach 2:
The storage latches themselves serve the function of maintaining state information during power reduction mode without requiring continuous active buffering. Once the state is transferred to storage latches, they autonomously retain the information using minimal power, making the system self-sufficient during low-power periods.
Data Source
AI summary
A state retention circuit for retaining the state of a data storage element during a power reduction mode including a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled from between first and second states before entering the power reduction mode so that the storage latch latches the state of the data storage element. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention transistor is overpowered when the retention node is pulled to the second state in which the retention inverter quickly turns off the retention transistor. When the retention node is toggled back to the first state, the retention inverter keeps the retention transistor turned on during the power reduction mode.