State Retention Circuit With Scan Parity Integrity Check
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Solution Overview
Problem
Data processing systems face challenges in maintaining state integrity during low power modes due to vulnerability to soft errors, which existing techniques attempt to address through voltage margins and additional circuitry, but these solutions increase power consumption and circuit area.
Innovation Solution
A state retention component that generates a parity value based on its state value and scan input value, allowing the parity value to invert if either changes, enabling the detection of errors within a scan chain and providing a mechanism to monitor state integrity without significant power overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage margin is increased to provide resistance to soft errors, then reliability is improved, but power consumption increases
Solution Approach 1:
The state retention component monitors its own state integrity by generating a parity value from its internal state value and comparing it with an expected parity value, eliminating the need for external monitoring circuits or increased voltage margins
Solution Approach 2:
The component generates feedback in the form of a parity value that reflects the current state integrity, allowing the system to detect errors and take corrective action without continuously consuming additional power
2Reliability
If canary circuits are provided to support state retention integrity, then reliability is improved, but circuit area and power consumption increase
Solution Approach 1:
The parity generation function is merged with the existing state retention component, combining the state holding function and the integrity monitoring function into a single unit, thereby eliminating the need for separate canary circuits
Solution Approach 2:
The state retention component is made multi-functional by enabling it to both retain state values and generate parity information for error detection, allowing a single component to serve dual purposes
3Manufacturing precision
If scan path is used to load test patterns, then manufacturing precision is improved, but the scan output cannot simultaneously provide state integrity information
Solution Approach 1:
The scan output is made dynamic by enabling it to provide different information depending on the operational mode - test patterns during manufacturing testing and parity values during normal operation, maximizing the utility of a single output pin
Data Source
AI summary
A state retention component is provided which is configured to form part of data processing circuitry. The state retention component is configured to hold a state value at a node of the data processing circuitry when the data processing circuitry enters a low power mode. The state retention component comprises a scan input, wherein the state retention component configured, when a scan enable signal is asserted, to read in the state value from a scan input value applied at the scan input, and a scan output, wherein the state retention component is configured, when the scan enable signal is asserted, to read out the state value to the scan output. When the scan enable signal is not asserted, the state retention circuit outputs at the scan output a parity value, wherein the parity value is generated by combinatorial function circuitry on the basis of the state value and the scan input value, wherein the combinatorial function circuitry is configured such that the parity value inverts if either the state value or the scan input value changes, thus providing an external indication of the integrity of the state value held by the state retention component.