State Retention Circuit With Positive Feedback for Single DC Startup
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Solution Overview
Problem
Conventional state definition and retention circuits in integrated circuits face issues with multiple DC solutions during power supply ramp-up, leading to undesired static current and duty cycle distortion, making them unsuitable for data path usage.
Innovation Solution
A state definition and retention circuit utilizing two cross-connected PMOS transistors, NMOS transistors, and an inverter circuit, which creates a positive feedback to ensure a single DC solution by controlling voltage across connection nodes, avoiding back-to-back inverter configurations that cause multiple DC solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional state definition and retention circuits are used, then state retention is achieved, but multiple DC solutions occur during power supply ramp-up causing static current and duty cycle distortion
Solution Approach 1:
The patent introduces a positive feedback mechanism through a specific transistor configuration where the output of the inverter circuit is fed back to the gate of the first PMOS transistor. This feedback ensures that during power supply ramp-up, the circuit quickly establishes a single stable DC state by reinforcing the voltage at connection node VX, preventing the multiple DC solutions that cause static current and duty cycle distortion while maintaining reliable state retention.
2Reliability
If conventional state definition and retention circuits are used, then state retention is achieved, but multiple DC solutions occur during power supply ramp-up causing duty cycle distortion
Solution Approach 1:
The positive feedback through the inverter circuit and transistor configuration ensures rapid and decisive state transitions during power supply ramp-up. By reinforcing the voltage at connection node VX, the feedback mechanism eliminates the ambiguous multiple DC solutions that cause duty cycle distortion, ensuring clean, well-defined duty cycles while maintaining state retention reliability.
3Reliability
If back-to-back inverter configurations are used, then state retention is achieved, but multiple DC solutions occur during power supply ramp-up
Solution Approach 1:
The patent replaces the conventional back-to-back inverter configuration with a transistor-based positive feedback circuit. This new configuration actively reinforces a single DC state during power supply ramp-up by feeding back the output signal to the gate of the first PMOS transistor, ensuring voltage at connection node VX stabilizes to a unique value. This eliminates the multiple DC solutions inherent in back-to-back inverter configurations while maintaining state retention.
Solution Approach 2:
The patent changes the operational parameters of the circuit by using specific transistor sizing ratios and power supply voltage relationships. The first PMOS transistor is sized to provide sufficient drive strength during power supply ramp-up, and the power supply voltage is maintained above a threshold level. These parameter changes ensure that the positive feedback mechanism effectively establishes a single stable DC state, improving DC solution uniqueness compared to conventional configurations.
Data Source
AI summary
State definition and retention circuits are described. In one embodiment, a circuit includes two cross-connected PMOS transistors, first, second, and third NMOS transistors coupled to the PMOS transistors, an inverter circuit, and an output transistor connected to the PMOS transistors and to an output terminal of the circuit. The second NMOS transistor is connected to an input terminal of the circuit. A drain terminal and a gate terminal of the third NMOS transistor are connected to gate terminals of the PMOS transistors. The inverter circuit is coupled to the first and second NMOS transistors and to the input terminal. The inverter circuit is connected between a first power supply and a first base voltage. The PMOS transistors, the NMOS transistors, and the output transistor are connected between a second power supply and a second base voltage. Other embodiments are also described.