State-retentive Scan Latch for Low Leakage Standby Power
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Solution Overview
Problem
Integrated circuits face challenges in reducing standby leakage current while maintaining the ability to upload and download volatile states efficiently, especially in scan designs where power management is critical.
Innovation Solution
The implementation of a low leakage latch coupled with a de-powerable memory element, utilizing thick gate oxide MOSFET transistors and a bi-directional pass gate, allows for efficient state transfer and power management through active-to-low signals and non-overlapping scan clocks, reducing power consumption by adjusting voltage levels during standby modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard D-type flip-flops are used in scan chains, then state elements can be easily tested and scanned, but standby leakage current increases due to continuous power consumption
Solution Approach 1:
The scan latch is divided into two separate memory elements: a first memory element (de-powerable) and a second memory element (low-leakage). This segmentation allows the first element to be powered down during standby while the second element maintains state retention with minimal leakage, thus reducing overall power consumption while preserving scan functionality.
Solution Approach 2:
Different memory elements are assigned different power management characteristics based on their functional requirements. The first memory element uses de-powering for maximum leakage reduction, while the second memory element uses low-leakage design for state retention. This local differentiation optimizes power consumption without compromising scan chain reliability.
2Loss of energy
If de-powering is used to reduce leakage current, then power consumption decreases, but the ability to retain and transfer state information is compromised
Solution Approach 1:
Before the first memory element is de-powered, its state is预先 transferred to the second memory element. This preliminary action ensures that state information is preserved in the low-leakage second element before power is removed from the first element, preventing information loss while enabling leakage reduction.
Solution Approach 2:
The second memory element acts as an intermediary that receives state information from the first memory element before de-powering occurs. This intermediary structure allows the first element to be de-powered for leakage reduction while the second element maintains the state information, thus mediating between power reduction and information retention requirements.
3Loss of energy
If thick gate oxide MOSFET transistors are used in the low leakage latch, then leakage current is reduced, but drive capability decreases
Solution Approach 1:
Thick gate oxide transistors are used specifically in the low-leakage second memory element and latch circuitry where leakage reduction is critical, while the first memory element uses standard transistors optimized for drive capability. This local application of thick gate oxide technology reduces leakage in critical paths without compromising overall drive capability.
Data Source
AI summary
A device can include 1) a sustained or constantly powered low leakage latch to and from which a volatile state is uploaded and downloaded, respectively, based on an active-to-low signal, and 2) an intermittently powered or de-powerable memory element, coupled to the low leakage latch, from which and to which the volatile state is uploaded and downloaded, respectively, based on the active-to-low signal and a de-powerable voltage across the de-powerable memory element is powered and un-powered, respectively.