Static Address Mapping for Programmable Logic Peripherals
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Solution Overview
Problem
In integrated circuits with programmable logic, the variability in address mapping for peripherals across different instantiations of a design leads to complexity and error-prone management, as address ranges change with each instantiation, making it difficult to maintain consistency across different systems, software versions, and platforms.
Innovation Solution
A method for generating static address maps by obtaining and assigning predefined static address ranges to circuit blocks within the integrated circuit, ensuring consistent address mapping for peripherals across various platforms and software versions, thereby facilitating predictable and deterministic address slot generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If random address assignment is used for circuit blocks in programmable logic devices, then flexibility and adaptability of the PLD platform are improved, but design management complexity and error-proneness increase
Solution Approach 1:
The patent applies preliminary action by pre-assigning static addresses to circuit blocks during the device architecture design phase, before actual design instantiation. This creates a predetermined address map that remains consistent across all design instantiations, eliminating the need to reassign addresses with each design change while preserving PLD flexibility.
Solution Approach 2:
The patent changes the address assignment parameter from dynamic (random) to static (fixed). By modifying how addresses are assigned - from being generated randomly at instantiation time to being predetermined in the device architecture - the patent resolves the contradiction between flexibility and management complexity.
2Stability of the object's composition
If address ranges are reassigned with each design instantiation, then consistency across different instantiations is improved, but variability and error-proneness increase
Solution Approach 1:
By performing address assignment in advance during device architecture design rather than at each instantiation, the patent ensures both consistency and reliability. The static address map is established once and reused across all instantiations, eliminating variability while maintaining systematic management.
3Device complexity
If static address mapping is implemented, then design management complexity is reduced and consistency is improved, but flexibility of the PLD platform is reduced
Solution Approach 1:
The patent resolves this contradiction by performing address assignment in advance during device architecture design. This preliminary action creates a static address map that simplifies design management while the PLD retains its inherent flexibility through programmable logic resources that can be configured for different functions.
Solution Approach 2:
The patent changes the address assignment parameter from dynamic to static, reducing design management complexity. The flexibility of the PLD platform is preserved through the programmable nature of the logic resources, which can be configured for different functions despite having fixed addresses.
4Adaptability or versatility
If different address maps are generated for different systems, then adaptability to specific platforms is improved, but interoperability and software portability are reduced
Solution Approach 1:
The patent applies universality by creating a standardized static address map that can be used across multiple platforms and systems. This universal address mapping approach allows software to be portable across different PLD implementations while each platform maintains its specific characteristics through programmable logic configuration.
Data Source
AI summary
Address map generation is described. More particularly, static addresses are obtained. A system design at least a portion of which is for instantiation in configurable logic of an integrated circuit is obtained. The system design includes a processor. At least one predefined circuit block in the design is identified as a peripheral connected to a processor. The at least one predefined circuit block is for instantiation in the configurable logic of the integrated circuit. Assigned to the at least one predefined circuit block is a static address range which is obtained from the static addresses. An address map for the design is generated having the at least one predefined circuit block with the static address range. Thus, for example, independent designers designing separate systems having a same set of peripherals may map to the same static address ranges independent of software system builder tool version, board, or processor used.


