Static CAM Summary Circuit Without Pre-Charge Match Lines

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Solution Overview

Problem

Dynamic Content-Addressable Memories (CAMs) are slow, prone to noise, cause timing issues, and require additional circuitry and high power due to dynamic match line charging and discharging, leading to current leakages and weak capacitive coupling.

Innovation Solution

The implementation of a summary circuit with multiple levels of logic gates, including NAND and NOR gates, that eliminates the need for pre-charge circuitry, allowing for higher frequency operation and efficient data lookup without current leakage, by using transistors to manage current flow based on input logic states.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If dynamic match line charging and discharging is used in CAM, then data lookup function is achieved, but operation speed decreases and timing issues occur

Engineering Contradiction:
Improveoperation speedVSAvoidcircuitry complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent extracts and removes the pre-charge circuitry from the CAM cell design, eliminating the need for dynamic match line charging and discharging operations. This extraction of the pre-charge function resolves the contradiction by enabling faster operation speeds while reducing circuitry complexity and timing issues associated with dynamic charging/discharging cycles.

Inventive Principle:
Principle #2Taking out (Extraction)

2Use of energy by moving object

If pre-charge circuitry is used in dynamic CAM, then match line operation is enabled, but power consumption increases

Engineering Contradiction:
Improvepower consumptionVSAvoidmatch line operation
Core Design Contradiction:
Use of energy by moving objectVSEase of operation

Solution Approach 1:

The patent removes the pre-charge circuitry that was responsible for high power consumption in dynamic CAM operations. By extracting this power-intensive component, the invention achieves lower power consumption while maintaining match line operation through alternative static logic gate-based comparison mechanisms that do not require continuous charging and discharging cycles.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If dynamic match line is used in CAM, then data comparison is achieved, but current leakage occurs

Engineering Contradiction:
Improvedata comparison reliabilityVSAvoidcurrent leakage
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent converts the harmful effect of dynamic match line current leakage into a benefit by transitioning to a static logic gate-based comparison system. The static nature of the new design eliminates continuous charging and discharging operations that caused current leakage, thereby improving reliability of data comparison while reducing energy loss through the elimination of the dynamic match line mechanism.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

4Device complexity

If pre-charge circuitry is included in CAM, then match line initialization is achieved, but device complexity increases

Engineering Contradiction:
Improvecircuitry complexityVSAvoidmanufacturing simplicity
Core Design Contradiction:
Device complexityVSEase of manufacture

Solution Approach 1:

The patent extracts and eliminates the pre-charge circuitry from the CAM design, thereby reducing device complexity and making manufacturing simpler. The removal of this additional circuitry reduces the number of components that need to be manufactured and assembled, directly improving ease of manufacture while maintaining data comparison functionality through the static logic gate approach.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS8760900B2Content addressable memory
Publication Date: 2014.06.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8760900B2 patent drawing
  • US8760900B2 patent drawing
  • US8760900B2 patent drawing

AI summary

A memory includes a plurality of content-addressable memory (CAM) cells and a summary circuit associated with the plurality of CAM cells. The summary circuit includes a first level of logic gates and a second level of logic gates. The first level of logic gates have inputs each configured to receive an output of a corresponding one of the plurality of CAM cell. The second level of logic gates have inputs each configured to receive an output of a corresponding one of the first level of logic gates.