Static Checker Tool for Circuit Power Intent Validation
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Solution Overview
Problem
Current circuit simulation software is inadequate for validating complex electronic systems beyond ASICs and SoCs, as it cannot efficiently handle the increased complexity and diverse components found in larger systems like SSDs, PCBs, and cars, due to limitations in the unified power format (UPF) and static checking tools.
Innovation Solution
The method involves defining a power intent architecture for electronic circuits with additional attributes and parameters for pins, such as input and output voltages, currents, timing, and tolerances, and using a static checker tool to validate these attributes against a netlist representation, enabling the validation of larger systems by extending the UPF file format and adding rules for component attributes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the static checking tool checks for additional attributes and parameters beyond basic voltage and connection type, then the validation comprehensiveness is improved, but the computing time required substantially increases
Solution Approach 1:
The validation process is divided into multiple passes or stages, where critical attributes like voltage and connection type are checked first, followed by optional additional attributes. This segmentation allows the tool to provide comprehensive validation when needed while enabling faster checks for routine validations.
Solution Approach 2:
The tool implements a tiered checking approach where only essential attributes are checked by default, and additional attributes can be selectively enabled. This partial action approach ensures that the most important validations are always performed while allowing users to extend checking to additional parameters only when necessary, avoiding substantial computing time increases for routine validations.
2Adaptability or versatility
If the simulator is extended to accommodate larger systems with greater complexity, then the adaptability is improved, but the computational resources and time required substantially increase
Solution Approach 1:
The static checking tool is designed with a universal architecture that can handle both simple ASIC circuits and complex larger systems with diverse components. The tool's ability to work with extended UPF file formats and support multiple attribute types enables it to function across different system scales without requiring separate specialized tools, thus improving adaptability while managing computational complexity through efficient algorithms.
3Measurement precision
If the UPF file format is extended to include additional attributes and parameters, then the measurement precision is improved, but the device complexity increases
Solution Approach 1:
The extended UPF file format implements local quality by allowing different levels of detail and attribute specification for different components and contexts. Critical components can have detailed attribute definitions including multiple parameters, while less critical components can use simplified definitions. This selective detail approach improves measurement precision where needed without uniformly increasing file format complexity across the entire system.
Data Source
AI summary
A method for validating the design of an electronic circuit uses a static checker tool to verify the circuit design against rules and attributes of the components of the circuit. A power intent of the circuit, pins for power, ground and data signal inputs and outputs for each component, and a model for attributes and parameters of the pins are defined. The attributes of the components are defined in terms of input and output voltages; input and output currents; input and output voltage, current and data signal timing; and input and output voltage and current ranges and tolerances. A netlist of interconnections representing the designed circuit is validated against the power intent and the model for the attributes. A report is output describing the validity of the circuit based on the compatibility of the netlist, the power intent, and the model for the attributes of the components.