Static CMOS Full Adder Layout With Lower Capacitance and Delay
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Solution Overview
Problem
Conventional CMOS-based mirror full adders in SoCs have high transistor counts, leading to increased area and power consumption, which is undesirable for modern AI/ML applications, and result in reduced performance due to high input capacitance and delay.
Innovation Solution
A CMOS-based Full Adder circuit design that reduces the number of transistors by optimizing the sum and carry output generation circuits using exclusive-NOR, OR-AND-INVERT, and NAND gates, limiting each input pin to no more than 4-5 transistors, thereby reducing input capacitance and overall delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional CMOS-based mirror full adder is used, then the full adder can be implemented with standard circuit topology, but the transistor count increases to 28, leading to increased area and power consumption
Solution Approach 1:
The patent extracts and removes redundant transistors from the conventional full adder circuit. Specifically, it eliminates unnecessary transistors in the sum generation path by using alternative logic implementations (XNOR gates followed by XOR operations) that require fewer transistors, reducing the total count from 28 to 24-25 transistors while maintaining full adder functionality.
Solution Approach 2:
The patent changes the logical parameters and circuit topology of the full adder. It modifies the sum generation path by introducing XNOR gates and reconfiguring the logic stages, transforming the circuit from a conventional 3-MOS-stack design to an optimized structure with reduced transistor count and improved performance characteristics.
2Ease of manufacture
If conventional CMOS-based mirror full adder with 3 MOS stacking is used, then the circuit can be implemented with standard design, but the delay increases due to degraded performance in sum and carry output arcs
Solution Approach 1:
The patent segments the sum generation path into distinct logical stages using XNOR gates followed by XOR operations. This segmentation allows each stage to be optimized independently, reducing the cumulative delay compared to the conventional 3-MOS-stack approach where all transistors are stacked in series, creating a longer critical path.
Solution Approach 2:
The patent inverts the conventional approach by using XNOR gates (which naturally produce the correct logic for sum generation when combined with carry-in) rather than the traditional AND-OR logic. This inversion of the logical approach reduces the number of series transistor stacks and thereby reduces delay.
3Ease of manufacture
If conventional CMOS-based mirror full adder is used, then the full adder can be implemented with standard circuit, but the input capacitance increases due to multiple MOS transistors connected to each input pin
Solution Approach 1:
The patent extracts and removes redundant transistor connections to input pins. In the optimized design, each input pin (A, B, CI) is connected to fewer transistors compared to the conventional design, directly reducing the input capacitance and improving the driving capability of preceding stages.
4Ease of manufacture
If 28 transistors are used in full adder circuit, then the conventional design can be implemented, but the area consumption increases which is undesirable for modern SoC
Solution Approach 1:
The patent extracts and removes 3-4 redundant transistors from the conventional full adder circuit, directly reducing the transistor count from 28 to 24-25. This extraction of unnecessary components proportionally reduces the circuit area while maintaining the full adder's functional capabilities.
Solution Approach 2:
The patent merges certain logic functions into more efficient gate structures. By combining the sum generation logic into a streamlined sequence of XNOR and XOR gates, and optimizing the carry generation logic, the overall circuit area is reduced compared to the conventional separate AND-OR implementation.
Data Source
AI summary
Provided is an apparatus that includes an integrated circuit including a static complementary metal-oxide-semiconductor based full adder (FA) circuit. The FA circuit comprises a sum generation circuit configured to generate a sum output and a carry output generation circuit configured to generate a carry output. The sum generation circuit comprises a first exclusive-NOR gate and a second exclusive-NOR gate. The carry output generation circuit comprises a first or-and-invert (OAI) gate, a second OAI gate, and a NAND gate. The first OAI gate is configured to receive an output of the NAND gate to generate one of an exclusive-NOR output or a NOR output of a first operand and a second operand. The second OAI gate is configured to receive the output of the NAND gate, an inverse of a carry input, and the generated one of the exclusive-NOR output or the NOR output to produce the carry output.