Static CMOS Multi-Output Logic Gates With Shared Transistors
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Solution Overview
Problem
Conventional multiple-output domino logic circuits face challenges such as leakage, coupling, process variation, supply noise, clock skew, and increased area and power consumption due to the need for multiple logic gates to perform multiple logic functions, which complicates their use in integrated circuits.
Innovation Solution
The development of multiple-output static CMOS logic gates that share transistors to compute multiple logic functions from a common set of inputs, reducing the number of transistors required and minimizing area and power consumption, while also addressing the issues encountered in domino circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple logic gates are used to produce multiple outputs, then the logic functions can be performed, but the area and power consumption increase in proportion to the number of transistors
Solution Approach 1:
The patent combines multiple logic gates into a single integrated circuit structure where transistors are shared across multiple logic functions. The pull-down network and pull-up network are merged to compute multiple outputs simultaneously, reducing the total transistor count compared to using separate logic gates for each function.
Solution Approach 2:
The invention creates a universal logic gate structure that can compute multiple logic functions (such as AND, OR, NAND, NOR) from a common set of inputs. The same transistor network serves multiple outputs, making the circuit multi-functional and reducing the need for dedicated transistors for each logic function.
2Adaptability or versatility
If multiple logic gates are used to produce multiple outputs, then the logic functions can be performed, but the power consumption increases in proportion to the number of transistors
Solution Approach 1:
The patent merges multiple logic gates into a single structure with shared transistors, reducing the total number of active devices that consume power. The pull-down and pull-up networks are integrated to serve multiple outputs simultaneously, lowering the overall power consumption compared to multiple separate gates.
Solution Approach 2:
The universal logic gate structure allows a single transistor network to perform multiple logic functions, reducing the total transistor count and consequently the power consumption. The same transistors are reused across different logic functions, minimizing energy waste.
3Area of stationary object
If domino logic gates are used to share transistors for multiple outputs, then the area is reduced, but the circuit becomes increasingly difficult to use due to leakage, coupling, process variation, supply noise, clock skew, and productivity issues
Solution Approach 1:
The patent inverts the approach by using static CMOS logic instead of domino logic. This reversal eliminates the need for clock signals and precharge transistors, removing the sources of clock skew and timing issues. The static logic maintains stable outputs without the leakage and coupling problems inherent in domino logic.
Solution Approach 2:
The invention uses simple, robust static CMOS transistor structures that are easier to manufacture and more reliable than complex domino logic circuits. The static logic gates use straightforward pull-down and pull-up networks that are less sensitive to process variations and supply noise, improving overall circuit reliability.
Data Source
AI summary
An approach is provided in embodiments of the present invention for building multiple-output static CMOS logic gate circuits that share transistors when computing multiple functions from a common set of inputs. In particular, an approach is provided which includes building multiple-output static NAND gates that compute the subfunctions of three or more inputs and building multiple-output static NOR gates that compute the subfunctions of two or more inputs. The approach also includes building multiple-output static XOR-XNOR gates that are capable of computing two-input XOR, three-input XOR, two-input XNOR, and three-input XNOR, and building multiple-output static Propagate-Generate (PG) compound gates. The approach further includes building carry propagate adders, priority encoders, binary-to-thermometers, decoders, etc. that are capable of using the multiple-output static gates embodied in the present invention.