Static Dataflow Processor for Affine Image Transform Throughput
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Solution Overview
Problem
Conventional CPUs and GPUs incur significant overhead due to dynamic reconfiguration and implicit instruction dependencies when performing affine transformations on images, which affects the efficiency and feasibility of training neural networks and other applications requiring numerous image transformations.
Innovation Solution
A statically reconfigurable dataflow architecture processor (SRDAP) performs N-dimensional affine transformations using a dataflow program that statically configures vector compute datapaths and scratchpad memories, eliminating the need for dynamic instruction fetching and handling of implicit dependencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional CPUs and GPUs are used to perform affine transformations, then the transformations can be performed with flexible programming, but significant overhead is incurred due to dynamic reconfiguration and implicit instruction dependencies
Solution Approach 1:
The patent applies dynamics by enabling the processor to switch between static reconfiguration for high-performance applications and dynamic reconfiguration for flexibility, resolving the contradiction between adaptability and productivity through conditional operational modes
Solution Approach 2:
The processor is segmented into multiple independent processing elements that can operate in parallel, with each element having its own configuration, allowing simultaneous execution of multiple transformations without implicit dependencies, thus improving productivity while maintaining programming flexibility through high-level language support
2Productivity
If static reconfiguration is used to eliminate dynamic instruction fetching, then overhead is reduced and throughput is improved, but the device complexity increases due to explicit computation graph mapping
Solution Approach 1:
The patent introduces a compiler as an intermediary that automatically translates high-level programming languages into explicit computation graphs and maps them to the hardware architecture, eliminating the need for manual hardware configuration while achieving static reconfiguration benefits, thus improving throughput without exposing users to hardware complexity
Solution Approach 2:
The patent replaces manual hardware configuration mechanisms with automated software compilation mechanisms, substituting the mechanical process of explicit computation graph mapping with an automated compiler-driven process that generates equivalent hardware configurations from high-level code
3Speed
If multiple scratchpad memories are used to store replicated copies of input image, then parallel processing is enabled and transformation speed is improved, but the quantity of memory resources increases
Solution Approach 1:
The patent segments the memory system into multiple independent scratchpad memories, each storing a replicated copy of the input image, allowing parallel processing elements to access different copies simultaneously, thus improving transformation speed while distributing memory resources across multiple units rather than requiring one large memory
Data Source
AI summary
A statically reconfigurable dataflow architecture processor (SRDAP) performs an N-dimensional affine transform specified by a matrix on an input image to produce an output image includes L address pattern memory units (PMUs) comprising a memory arranged as a vector of L banks, and L corresponding data PMUs. Each data PMU receives a copy of the input image.