Static Memory Cell Tristate Inverter Write Interference
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Solution Overview
Problem
Static random access memories face challenges with write-in interference during data writing and reading operations, leading to electrical leakage and potential data loss due to stringent manufacturing restrictions and read/write interference phenomena.
Innovation Solution
A static memory cell design incorporating a data latch circuit with first and second tristate output inverting circuits, where the data write-in circuit provides reference voltages to selected tristate output inverting circuits, disabling non-selected circuits to prevent interference during write-in operations, thus ensuring stable data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the minimum size in the manufacturing process is reduced to increase memory density, then manufacturing precision is improved, but write margin and electrical leakage resistance deteriorate due to read/write interference
Solution Approach 1:
The memory cell is divided into two separate write-in circuits (first write-in circuit and second write-in circuit) that operate independently at different time periods. The data latch circuit is segmented into multiple tristate output inverting circuits that can be selectively activated. This segmentation allows write operations to be performed sequentially without interference, resolving the electrical leakage problem while maintaining the benefits of reduced minimum size for increased density.
2Speed
If conventional read/write operations are performed in static memory cells, then data access speed is maintained, but electrical leakage occurs due to read/write interference phenomenon
Solution Approach 1:
The patent implements periodic action by dividing write-in operations into distinct time periods: a first write-in time period for writing to the first tristate output inverting circuit, and a second write-in time period for writing to the second tristate output inverting circuit. During each time period, only the selected circuit is active while the other is disabled, eliminating simultaneous read/write interference and preventing electrical leakage while maintaining data access speed.
3Productivity
If data writing and reading operations are performed simultaneously in half-selected memory cells, then operational efficiency is maintained, but data loss occurs due to write-in interference
Solution Approach 1:
The patent applies preliminary action by disabling the non-selected write-in circuit before the write operation begins. The control circuit selectively enables either the first or second write-in circuit based on the write-in signal, ensuring that only the intended memory cell is affected. This preliminary isolation prevents write-in interference from propagating to half-selected cells, eliminating data loss while maintaining operational efficiency through selective activation.
Data Source
AI summary
A static memory apparatus and a static memory cell thereof are provided. The static memory cell includes a data latch circuit, a data write-in circuit and a data read-out circuit. The data latch circuit has a first tristate output inverting circuit and a second tristate output inverting circuit. The data write-in circuit provides a first reference voltage to a power receiving terminal of a selected tristate output inverting circuit which is one of the first and second tristate output inverting circuits, and provides a second reference voltage to an input terminal of the selected tristate output inverting circuit during a data write-in time period. The data read-out circuit generates read-out data according to a voltage at an output terminal of the second tristate output inverting circuit and the second reference voltage during a data read-out time period.