Static MMU Page Table for Cache Coherence Latency
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Solution Overview
Problem
In multi-processor systems, the dynamic nature of cached Translation Lookaside Buffers (TLBs) leads to cache coherence issues and increased latency due to the need for MMUs to consult complete page address tables for address translation and privilege checks, resulting in potential unauthorized data access and system stalls.
Innovation Solution
Implementing a static or quasi-static complete page address table within the Memory Management Unit (MMU) in RAM, eliminating the need for cached TLBs and reducing latency by using a variable page size page address table that resides entirely within hardware without content addressable memory (CAM) or extra comparators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If cached TLBs are used for address translation, then address translation speed is improved, but cache coherence issues and latency increase in multi-processor systems
Solution Approach 1:
The patent extracts the translation table from cache memory and places it directly in the MMU hardware. This removes the cached translation buffer (TLB) that causes coherence problems, while maintaining fast translation through direct hardware access to the translation table stored in on-chip memory within the MMU.
Solution Approach 2:
The patent introduces an intermediary uncached translation table structure that sits between the CPU and main memory, managed by the MMU. This intermediary table provides translation functionality without the cache coherence issues of traditional TLBs, as it is explicitly managed and synchronized by the MMU hardware.
2Measurement precision
If complete page address tables are consulted for address translation, then translation accuracy is improved, but latency increases
Solution Approach 1:
The patent segments the complete page address table into smaller translation table structures that can be stored in on-chip memory within the MMU. This segmentation allows the MMU to maintain complete translation information for faster access without requiring consultation of the entire large page table in main memory.
Solution Approach 2:
The patent moves the translation table from main memory to on-chip memory within the MMU, changing the spatial dimension of storage. This dimensional change from off-chip to on-chip memory provides both complete translation accuracy and reduced latency through faster access times.
3Reliability
If uncached static translation tables are used, then cache coherence issues are eliminated, but address translation speed may decrease
Solution Approach 1:
The patent replaces the software-managed cached TLB system with a hardware-managed uncached translation table system. The MMU hardware directly manages the translation table in on-chip memory, eliminating the need for cache coherence protocols and software intervention, thereby maintaining both reliability and speed.
Data Source
AI summary
A network unit, comprising a processor and a random access memory (RAM) component coupled to the processor, wherein the RAM component comprises a memory management unit (MMU) and a data RAM, wherein the MMU comprises a complete page address table for translating a virtual memory address received from the processor into a physical memory address, and wherein the complete page address table is substantially static.