Static Multicycle Path Setting From RTL and Netlist Analysis
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Solution Overview
Problem
Existing methods for setting multicycle paths in semiconductor integrated circuits require verification patterns, leading to insufficient logic verification and heavy workloads, making it difficult to accurately set multicycle paths.
Innovation Solution
A data processing device that performs static analysis on RTL data or net lists to extract transition pause storage elements and connection-source storage elements, determining multicycle paths without using verification patterns, and generates multicycle path constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic verification using verification patterns is performed to detect multicycle paths, then multicycle paths can be detected, but the workload becomes heavy and verification may be insufficient when patterns are inadequate
Solution Approach 1:
The invention extracts multicycle path information directly from RTL data and netlists by analyzing storage element connections and signal transition characteristics, removing the need for separate verification pattern processes. This extraction approach achieves accurate detection without the heavy workload of traditional verification methods
Solution Approach 2:
The design automatically identifies multicycle paths through static analysis of its own RTL description and netlist data, without requiring external verification patterns or manual designer input. The system serves itself by deriving multicycle path constraints directly from the design specifications
2Reliability
If verification patterns are used to find signal transitions, then multicycle paths can be identified, but the designer's workload increases significantly
Solution Approach 1:
The system automatically performs static analysis on RTL data and netlists to identify storage elements with transition pauses of two or more clock cycles, eliminating the need for designer-provided verification patterns. The multicycle path constraints are generated automatically based on the analyzed signal transition characteristics
Solution Approach 2:
The invention performs preliminary static analysis on the RTL description and netlist data to pre-identify multicycle paths before implementation. This preliminary action extracts connection-source storage elements and transition pause storage elements, preparing the multicycle path constraints in advance without requiring additional designer effort during verification
Data Source
AI summary
A formal verification executing unit performs a static analysis of at least either of RTL data and a net list of a semiconductor integrated circuit having two or more storage elements connected thereto and operating based on a clock cycle, extracts, from the two or more storage elements, a storage element with a shortest time being equal to or more than two clock cycles among times in which no signal transition occurs as a transition pause storage element, and extracts, from the two or more storage elements, a storage element of a connection source of the transition pause storage element as a connection-source storage element. Also, the formal verification executing unit determines to set a multicycle path between the transition pause storage element and the connection-source storage element.