Static Performance Modeling for Emulation Accuracy
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Solution Overview
Problem
Current processor and memory emulation technologies face challenges in accurately modeling cache events and system interactions, leading to performance discrepancies between simulated and actual target performance, especially with cache-based architectures, which affects developer confidence and necessitates advanced emulation for visibility and optimization.
Innovation Solution
The development of enhanced debug and profiling capabilities, including stall cycle profiling, event profiling, cache viewer, and advanced event triggering, along with compression techniques for trace data and adaptive calibration of delay lines, to provide richer visibility and monitoring of system and memory behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If simulators are used to model cache events and system interactions, then development time is reduced, but performance modeling accuracy deteriorates (simulated performance can be 50-100% away from actual target performance)
Solution Approach 1:
The patent implements preliminary action by performing static analysis and generating performance models during the compilation phase, before the program is executed. The performance model is built in advance using abstract interpretation techniques, allowing developers to get performance estimates early in the development cycle without running actual simulations, thus reducing development time while maintaining reasonable accuracy for architectural changes.
2Measurement precision
If advanced emulation is implemented to provide visibility into system behavior, then performance modeling accuracy is improved, but device complexity increases
Solution Approach 1:
The patent extracts the performance modeling functionality from complex runtime emulation systems and implements it as a separate static analysis phase during compilation. By taking out the performance analysis from the execution path and performing it beforehand using abstract interpretation, the system achieves accurate performance modeling without adding complexity to the actual device or requiring advanced emulation infrastructure.
Solution Approach 2:
The patent creates a simplified abstract model (copy) of the program's execution behavior that captures essential performance characteristics without replicating the full complexity of the actual system. This abstract interpretation model copies only the necessary control flow and data flow information needed for performance estimation, avoiding the need for complex full-system emulation while maintaining modeling accuracy.
3Loss of information
If detailed monitoring and profiling capabilities are added to track system behavior, then visibility into system behavior is improved, but loss of time in the development cycle increases
Solution Approach 1:
The patent performs detailed system behavior analysis in advance during the compilation phase rather than during runtime development activities. By conducting static analysis and generating performance models beforehand, the system provides comprehensive visibility into system behavior without interrupting the normal development cycle, thus avoiding time loss while maintaining information completeness.
Data Source
AI summary
The timing stream is used to capture pipeline advances and to record stall cycles. Timing streams may be in standard or compressed formats. The stalls are traced concurrently with the PC trace. The data trace is used for holding the reasons for the external event. The timing stream also holds external event information, to assure cycle accuracy of the event being traced.