Static PLA Reset-Driven Logic for High-Speed Low-Power Operation
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Solution Overview
Problem
Existing programmable logic arrays (PLAs) face a trade-off between high operation speed and low power consumption, with dynamic PLAs having high power consumption and noise, and static PLAs having low operation speed.
Innovation Solution
A high-performance static PLA design that uses a reset signal to initialize and evaluate input signals, featuring an AND plane with pull-down transistors and an OR plane with an inverter, which disables and evaluates output signals based on the reset signal state, enabling efficient operation without clock signal dependency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a dynamic PLA is used to achieve high operation speed, then the operation speed is improved, but power consumption increases and noise is generated
Solution Approach 1:
The patent implements dynamic evaluation within a static PLA architecture by using pull-down transistors that can be selectively activated based on input conditions. The circuit dynamically evaluates product terms only when necessary (when select signals are active), rather than continuously evaluating all terms as in traditional dynamic PLAs. This dynamic behavior is achieved through the selective activation of pull-down transistors in response to input signals, allowing the static PLA to exhibit dynamic evaluation characteristics without requiring clocked operation throughout the entire circuit.
2Use of energy by moving object
If a static PLA is used to achieve low power consumption, then power consumption is reduced, but operation speed decreases
Solution Approach 1:
The patent segments the PLA operation into distinct functional regions: the AND plane with pull-down transistors for product term evaluation, and the OR plane for sum term evaluation. Each segment operates independently with optimized characteristics - the AND plane segment dynamically evaluates only necessary product terms using pull-down transistors, while the OR plane segment processes results in a controlled manner. This segmentation allows different parts of the circuit to operate at optimal speeds for their specific functions while maintaining overall low power consumption through the static architecture.
3Speed
If a dynamic PLA is used to achieve high operation speed, then operation speed is improved, but noise increases
Solution Approach 1:
The patent implements periodic evaluation action through the selective activation of pull-down transistors based on input conditions. Rather than continuous evaluation that generates constant noise, the circuit performs evaluation actions only when select signals indicate it is necessary. The pull-down transistors are activated periodically or selectively based on input patterns, enabling the circuit to achieve high-speed evaluation when needed while remaining in a low-noise static state during other periods. This periodic action pattern reduces overall noise generation compared to continuously operating dynamic PLAs.
Data Source
AI summary
A high-performance programmable logic array (PLA) includes an AND plane that is initialized when a reset signal is activated and that evaluates a plurality of input signals when the reset signal is inactivated; and or OR plane that receives output signals of the AND plane, that is disabled when one of the output signals is activated, and that evaluates the rest of the output signals of the AND plane to output a final result signal when the one of the output signals of the AND plane is inactivated. The PLA uses a reset signal as a driving signal, instead of a clock signal. Accordingly, it is possible to realize a PLA with both low power consumption and high operation speed.