Static Electricity Protection Circuit Balanced Discharge
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Solution Overview
Problem
Existing static electricity protection circuits for liquid crystal devices face challenges in effectively discharging both positive and negative charges, leading to asymmetric discharge capabilities and potential non-recoverable electrostatic damage due to differences in carrier mobility between p-type and n-type transistors.
Innovation Solution
A static electricity protection circuit design that includes two p-type and two n-type transistors, where the transistors become conducting state regardless of charge polarity, with capacitance differences in wiring configurations to ensure balanced discharge paths for positive and negative charges, eliminating asymmetric diversity and enhancing discharge capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single p-type transistor and a single n-type transistor are used in the static electricity protection circuit, then the circuit structure is simple, but the discharge capability is asymmetric and insufficient for large numbers of positive charges
Solution Approach 1:
The static electricity protection circuit is segmented into four transistors (two p-type transistors 310a, 310b and two n-type transistors 330a, 330b) arranged in a complementary symmetry configuration. This segmentation divides the discharge function into multiple parallel paths, allowing the circuit to handle both positive and negative charges effectively while maintaining balanced discharge capability for both charge polarities
Solution Approach 2:
The invention intentionally introduces asymmetry in the form of different capacitance values in the wiring connections. Specifically, the first wiring 321 has a different capacitance than the second wiring 322, which compensates for the inherent asymmetry in carrier mobility between p-type and n-type transistors. This controlled asymmetry balances the overall discharge performance for both positive and negative charges
2Device complexity
If only one p-type transistor and one n-type transistor are used, then the circuit is simpler, but the discharge paths are insufficient leading to asymmetric discharge performance
Solution Approach 1:
The invention merges two p-type transistors and two n-type transistors into a unified complementary symmetry configuration where all four transistors work together to provide discharge paths for both positive and negative charges. The transistors are connected such that they form parallel discharge paths, combining their capabilities to achieve symmetric discharge performance that neither single transistor could provide alone
Solution Approach 2:
The invention changes the parameter of transistor quantity from one of each type to two of each type, and introduces capacitance as a new parameter to control discharge balance. By adjusting the capacitance values in the wiring connections, the circuit parameters are optimized to achieve balanced discharge capability for both positive and negative charges, compensating for inherent physical asymmetries
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides stable and prompt discharge of static electricity, reducing the likelihood of non-recoverable electrostatic damage and improving the reliability of electro-optic and electronic devices by ensuring balanced discharge for both positive and negative charges.
Implementation Method 1
charges caused on the signal wiring 501 by static electricity are distributed to a path leading to the high electric potential 502 or a path leading to the low electric potential 503, whichever has become in a conducting state
Data Source
AI summary
In a static electricity protection circuit according to the invention, a first wiring is electrically connected to a drain of a first p-type transistor and a gate and a source of a first n-type transistor; a second wiring is electrically connected to a gate and a source of the first p-type transistor, a drain of the first n-type transistor, a drain of a second p-type transistor and a gate and a source of a second n-type transistor; and a third wiring is electrically connected to a gate and a source of the second p-type transistor and a drain of the second n-type transistor.