Static SPI Scheduling for Collision-Free Peripheral Communication
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Solution Overview
Problem
Peripheral controllers in vehicles often lack the capability for asynchronous communication and networking protocols, leading to inefficiencies in data exchange with peripheral devices.
Innovation Solution
Implementing a static schedule for data exchange using a microcontroller that asserts a chip select line during dedicated time windows for each peripheral controller, allowing synchronous communication through a bus with a predefined schedule table.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If asynchronous communication or networking protocols are used, then communication flexibility is improved, but device complexity increases beyond the capability of peripheral controllers
Solution Approach 1:
The system segments communication into dedicated time windows for each peripheral controller, with each window containing a sequence of transactions. This segmentation allows simple peripheral controllers to communicate effectively without requiring complex asynchronous communication capabilities, as each controller only needs to handle its specific time window with predefined transactions.
Solution Approach 2:
The communication system uses periodic time windows that are cyclically repeated, with each window dedicated to specific peripheral controllers. This periodic structure provides regular, predictable communication intervals that simplify the controller design while maintaining systematic data exchange across multiple peripherals.
2Productivity
If data exchange with multiple peripheral controllers occurs simultaneously, then communication efficiency is improved, but data collisions occur on the shared bus
Solution Approach 1:
The system implements cyclic time windows that periodically allocate specific time slots to different peripheral controllers. Within each cycle, multiple controllers can be serviced in sequence without collision, and the cyclic repetition ensures continuous efficient communication while maintaining data integrity through structured time separation.
Solution Approach 2:
The communication schedule is predetermined and stored in a schedule table, with each time window and transaction sequence predefined in advance. This preliminary structuring of communication patterns allows the system to efficiently manage multiple peripheral controllers without real-time arbitration, as the communication sequence is established beforehand to prevent collisions.
3Adaptability or versatility
If a dynamic communication schedule is implemented, then adaptability to different communication needs is improved, but processing overhead increases and blocks other processes
Solution Approach 1:
The communication schedule, including time window assignments and transaction sequences for each peripheral controller, is predetermined and stored in a schedule table. This preliminary configuration allows the system to adapt to different communication needs through the structured schedule while executing the communication protocol in a simplified, repeatable manner that minimizes processing overhead during actual data exchange.
Solution Approach 2:
The microcontroller automatically executes the predetermined communication sequence by retrieving transactions from the schedule table and performing them in the specified time windows without requiring complex real-time arbitration or dynamic decision-making. This self-service execution of the structured schedule reduces processing overhead and allows other processes to run concurrently without blocking.
Data Source
AI summary
A PCB has a plurality of peripheral controllers mounted to the PCB, each peripheral controller including one or more registers. A bus is secured to the PCB and including one or more data lines each data line of the one or more data lines coupled to each peripheral controllers of the plurality of peripheral controllers. A memory is mounted to the PCB. A microcontroller is mounted to the PCB and coupled to the memory and the bus. The microcontroller configured to transmit and receive data to each peripheral controller of the plurality of peripheral controllers according to a static schedule in which for each cycle of the static schedule, each time window of a plurality of time windows is statically dedicated to exchange of data with each peripheral controller of the plurality of peripheral controllers corresponding to each time window.