Static Ternary Gate Circuit With Pass Transistors for Low Static Power
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Solution Overview
Problem
Current ternary logic circuits lack an optimized synthesis technique, leading to inefficiencies in power consumption and complexity, particularly in static gates using diode-connected transistors which continuously consume power to maintain half-drain voltage.
Innovation Solution
A static ternary gate design utilizing single-walled carbon nanotube field effect transistors (CNTFETs) with a pass transistor-based structure, where transistors with different threshold voltages are used to manage voltage levels and current flow efficiently, reducing static power consumption by employing a body effect and minimizing transistor count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If diode-connected transistors are used to maintain half-drain voltage in static ternary gates, then voltage stability is improved, but static power consumption increases
Solution Approach 1:
The patent transitions from a static voltage maintenance approach using diode-connected transistors to a dynamic approach using pass transistors controlled by input signals. The pass transistors are turned on/off based on logic conditions, allowing voltage to be maintained only when needed, thereby eliminating continuous static power consumption while preserving voltage stability during active states.
Solution Approach 2:
The patent changes the operating state of the transistors from always-on (diode-connected) to conditionally-on (pass transistor mode). By controlling the gate voltage of pass transistors based on input signals, the circuit dynamically adjusts its power consumption and voltage maintenance behavior, achieving low power operation while maintaining necessary voltage levels.
2Ease of manufacture
If conventional ternary logic circuit synthesis techniques are used, then circuit implementation is simplified, but power consumption and complexity increase
Solution Approach 1:
The patent segments the ternary logic gate into distinct functional paths: a drain-ground path for full voltage swings and a half-drain path for reduced voltage transitions. This segmentation allows the circuit to selectively activate only the necessary path based on the required logic operation, minimizing unnecessary power consumption while maintaining ease of implementation through modular design.
Solution Approach 2:
The patent employs periodic or conditional activation of different transistor paths based on input signal states. Instead of continuous operation, the pass transistors are activated only when specific logic conditions are met, creating a periodic action pattern that reduces average power consumption while maintaining circuit functionality.
3Loss of energy
If pass transistor-based structure with body effect is used, then energy efficiency is improved, but device complexity increases
Solution Approach 1:
The patent utilizes the body effect, an inherent physical phenomenon in transistors, to automatically adjust threshold voltages based on source-body voltage differences. This self-service mechanism requires no additional control circuitry or external intervention, allowing the device to self-regulate its power consumption and voltage characteristics, thereby improving energy efficiency without significantly increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design significantly reduces static power consumption and improves energy efficiency by maintaining half-drain voltage with low static currents, achieving a power consumption reduction of up to 98.66% compared to conventional diode-connected transistor-based static gates.
Implementation Method 1
a first transistor configured to connect a node between the first pull-up circuit and the second pull-down circuit to an output terminal
Implementation Method 2
a second transistor configured to connect a node between the second pull-up circuit and the first pull-down circuit to the output terminal
Implementation Method 3
reducing static power consumption by employing a body effect
Implementation Method 4
transistors with different threshold voltages are used to manage voltage levels and current flow efficiently
Data Source
AI summary
A static ternary gate is disclosed. The static ternary gate includes a drain-ground path configured to output a drain voltage through a first transistor when a first pull-up circuit is turned on, and output a ground voltage through a second transistor when a first pull-down circuit is turned on, a half-drain path configured to output a half-drain voltage through the first transistor and the second transistor when both a second pull-up circuit and a second pull-down circuit are turned on. The first transistor is configured to connect a node between the first pull-up circuit and the second pull-down circuit to an output terminal, and the second transistor is configured to connect a node between the second pull-up circuit and the first pull-down circuit to the output terminal.