Static Timing Analysis Using Global Variation Parameters
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Solution Overview
Problem
Current static timing analysis methods, such as statistical static timing analysis (SSTA) and parameterized on-chip-variation (POCV) static timing analysis, are either time-consuming for library development and static timing analysis or fail to accurately reflect global variations in integrated circuit timing.
Innovation Solution
A method that loads a library with local and global variation information, calculates delays of timing arcs, and determines timing path violations using graph-based and path-based analyses, incorporating global variation parameters to improve accuracy and reduce analysis time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If statistical static timing analysis (SSTA) is used to reflect process variations, then timing analysis accuracy is improved, but library development time and analysis time increase significantly
Solution Approach 1:
The patent segments the timing analysis into two distinct parts: (1) a comprehensive SSTA-based analysis performed once during library development to generate detailed timing models and variation data, and (2) a streamlined analysis that uses these pre-computed models for rapid reuse in subsequent design iterations. This segmentation allows the time-consuming accurate analysis to be performed only once, while subsequent analyses benefit from pre-processed data.
Solution Approach 2:
The patent performs preliminary timing analysis and variation characterization during library development before the actual design timing analysis. By pre-computing timing models, variation statistics, and critical path information, the system prepares all necessary data structures and models in advance, eliminating the need to re-compute them during each design analysis cycle.
2Loss of time
If parameterized on-chip-variation (POCV) static timing analysis is used to reduce analysis time, then library development time is reduced, but global variation accuracy deteriorates
Solution Approach 1:
The patent merges the advantages of both SSTA and POCV approaches by combining pre-computed global variation models (from POCV) with detailed local timing models (from SSTA). The system integrates global process variation data with local timing arc information to create a comprehensive timing analysis model that captures both global and local effects simultaneously.
Solution Approach 2:
The patent creates a composite timing analysis model that combines different types of variation data: global process variation parameters, local timing arc variations, and their statistical relationships. This composite model structure allows the system to leverage both the speed of POCV and the accuracy of SSTA by integrating multiple data sources and modeling approaches into a unified framework.
3Reliability
If comprehensive timing analysis with full variation modeling is performed, then timing constraint verification accuracy is improved, but computational complexity increases
Solution Approach 1:
The patent extracts and separates the computationally intensive tasks from the routine verification tasks. By extracting global variation parameters and timing models during library development, the system removes the heavy computational burden from subsequent timing analyses, leaving only lightweight verification operations that check timing constraints against pre-computed models.
Solution Approach 2:
The patent changes the computational parameters by pre-computing and storing timing models with various variation conditions during library development. This allows subsequent analyses to use these pre-parameterized models rather than re-computing with full variation modeling, significantly reducing computational complexity while maintaining accuracy through the use of statistically representative pre-computed data.
Data Source
AI summary
A method of performing a static timing analysis on an integrated circuit includes loading a library that includes local random variation information of the integrated circuit and global variation information of the integrated circuit that is obtained based on a set of a plurality of global variation parameters of the integrated circuit, calculating delays of timing arcs included in the integrated circuit based on the library, and determining whether at least one timing path of a plurality of timing paths included in the integrated circuit violates a timing constraint based on the delays of the timing arcs in the at least one timing path, the local random variation information of the integrated circuit and the global variation information of the integrated circuit.