Static Timing Analysis With Flexible Noise And Delay Models
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Solution Overview
Problem
Current static timing analysis tools face challenges in accurately modeling noise effects and timing delays in integrated circuits with smaller transistor channels, as they fail to account for complex signal propagation and noise interactions effectively.
Innovation Solution
A flexible noise analysis method is introduced, using a multi-CCC current source model that concurrently analyzes noise and delay effects by partitioning the analysis into independently controlled components, including aggressor and victim driver models, filtering, virtual aggressor alignment, and objective measures, allowing for user-selectable methods to accurately compute noise impacts on circuit stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional static timing analysis tools are used, then basic timing delay estimation can be obtained, but accurate modeling of noise effects and signal propagation in circuits with smaller transistor channels is not achieved
Solution Approach 1:
The patent segments the noise analysis into multiple independent components: aggressor driver models, victim driver models, filtering mechanisms, virtual aggressor alignment, and objective measures. This segmentation allows each component to be analyzed and modeled separately, improving precision while managing complexity through modular structure.
Solution Approach 2:
The patent introduces a virtual aggressor driver as an intermediary element that models noise effects without requiring direct physical representation of all noise sources. This intermediary approach simplifies the modeling process while maintaining accuracy in capturing noise-induced timing variations.
2Measurement precision
If comprehensive noise and delay analysis is performed, then accurate timing estimation is achieved, but computational complexity and analysis time increase
Solution Approach 1:
The patent applies partial action by analyzing only the most critical noise sources and timing paths rather than performing exhaustive analysis of all possible noise interactions. The filtering mechanism identifies and prioritizes significant aggressor drivers, allowing accurate analysis of key factors while skipping less impactful computations to reduce overall analysis time.
Solution Approach 2:
The patent performs preliminary actions by pre-characterizing driver models and noise effects before the main timing analysis. The virtual aggressor driver is pre-configured with noise models, and alignment parameters are pre-computed, so that during actual timing analysis, these pre-prepared elements can be directly applied without time-consuming real-time calculations.
3Measurement precision
If detailed modeling of aggressor and victim drivers is implemented, then noise effects are accurately captured, but device complexity increases
Solution Approach 1:
The patent creates universal driver models that can represent both aggressor and victim drivers using similar structural frameworks. The same modeling techniques and component types are applied across different driver instances, allowing for accurate noise effect capture while reducing overall complexity through model reuse and standardization.
Data Source
AI summary
Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design may be partitioned into a plurality of circuit stages. A timing graph including timing arcs is constructed to represent the timing delays in circuit stages of the integrated circuit design. A model of each circuit stage may be formed including a model of a victim driver, an aggressor driver, a victim receiver, and a victim net and an aggressor net coupled together. For each timing arc in the timing graph, full timing delays may be computed for the timing arcs in each circuit stage.