Graph-Based Static Timing Analysis Pessimism Reduction
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Solution Overview
Problem
Graph-based static timing analysis (GBA) in integrated circuits introduces significant pessimism due to overestimation of delays, leading to excessive pessimistic slack values and increased development and verification efforts, power consumption, and chip area, especially with advanced on-chip variation analysis.
Innovation Solution
A method that identifies a subset of timing paths for path-based analysis, determining optimized GBA timing parameters by minimizing a function based on the difference between GBA and PBA parameters, using correction factors for circuit elements, and storing these factors for subsequent analyses to reduce pessimism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If global derating factor is applied to all cells and interconnects across the whole chip, then timing analysis can be performed efficiently with linear complexity, but this leads to overestimation of delays and excessively pessimistic slack values
Solution Approach 1:
The patent applies local quality by transitioning from a global derating factor applied uniformly across the entire chip to path-specific derating factors. Each timing path receives a customized derating factor based on its specific characteristics (depth, distance, number of transitions), allowing accurate delay estimation for each path without the excessive pessimism introduced by global derating. This resolves the contradiction by maintaining efficiency through automated path-specific analysis while achieving precise slack values.
2Measurement precision
If path-based static timing analysis is performed on all timing paths, then accurate timing analysis can be achieved, but this becomes infeasible for large circuits due to exponential complexity in runtime and memory overhead
Solution Approach 1:
The patent applies parameter changes by introducing a statistical approach that transforms the exact but computationally expensive path-based analysis into an efficient approximate method. By using derating factors based on path characteristics (depth, distance, transitions) and statistical timing parameters (mean and standard deviation), the method achieves acceptable accuracy without exponential complexity. The linear-time graph-based analysis framework with optimized derating provides a practical solution for large circuits.
3Reliability
If advanced on-chip variation analysis with path-based metrics is applied, then timing analysis accounts for on-chip variations, but this introduces large amounts of pessimism due to exaggerated derating factors from worst-case metrics
Solution Approach 1:
The patent applies feedback by using an iterative optimization process that adjusts derating factors based on comparing graph-based analysis results with path-based analysis results. The method computes initial derating factors, performs both GBA and PBA, compares the slack values, and refines the derating factors to minimize the difference between the two approaches. This feedback loop eliminates the excessive pessimism introduced by worst-case metrics while maintaining robustness to on-chip variations.
Solution Approach 2:
The patent applies partial action by selectively applying derating only to the extent necessary to account for on-chip variations, rather than using worst-case derating for all paths. The optimization process determines the minimal derating required to achieve accurate results, avoiding the excessive pessimism that would result from applying maximum derating factors uniformly across all timing paths.
Data Source
AI summary
The disclosure relates to a method, computer program product or data processing system for performing graph-based static timing analysis, GBA, of an integrated circuit design having a set of timing paths. The method comprises identifying a subset of the set of timing paths and performing path-based analysis, PBA, of the subset of timing paths to determine at least one PBA timing parameter for each timing path of the subset of timing paths. The method further comprises determining at least one optimized GBA timing parameter for at least one timing path of the subset of timing paths by minimizing a function that is based on a difference between the at least one optimized GBA timing parameter and the at least one PBA timing parameter of the at least one timing path.