Static Timing Analyzer Stage Delay Variation
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Solution Overview
Problem
Conventional static timing analysis techniques are inadequate in accurately determining the impact of local random variations on integrated circuits, leading to inefficient and inaccurate timing analysis, especially as transistor density increases and operating voltage decreases.
Innovation Solution
A static timing analyzer that determines stage delay variation by incorporating intrinsic delay, induced delay variation, and covariance delay terms, using a covariance module to calculate correlation between stages, and generating normal distributions from asymmetric delay distributions to improve accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If global derating parameters are used to model on-chip variation, then timing analysis can be performed efficiently, but the analysis becomes inaccurate because context or location regarding the delay is ignored
Solution Approach 1:
The patent applies local quality by transitioning from global derating parameters to local random variation models that capture context-specific delay characteristics. Each delay is modeled with location-dependent parameters (mean, standard deviation, skewness, kurtosis) that reflect local circuit conditions, enabling both efficient computation and accurate timing analysis that accounts for spatial variations in the circuit.
2Loss of time
If conventional STA techniques are used, then timing analysis can be performed on large ICs within reasonable time, but the impact of local random variations on overall circuit performance cannot be accurately determined
Solution Approach 1:
The patent applies parameter changes by extending the delay distribution from simple deterministic values to complex statistical distributions characterized by multiple parameters (mean, standard deviation, skewness, kurtosis). This allows the analysis to capture the impact of local random variations while maintaining computational efficiency through statistical moment propagation rather than exhaustive simulation.
3Quantity of substance
If transistor density increases and operating voltage decreases, then circuit integration is improved, but local random variation becomes increasingly important and conventional analysis becomes inadequate
Solution Approach 1:
The patent applies dynamics by making the delay characteristics adaptive and context-dependent rather than static. The statistical parameters (mean, standard deviation, skewness, kurtosis) are dynamically determined based on local circuit conditions, transistor characteristics, and operating voltage, allowing the analysis to accurately capture the increasing impact of local random variations as transistor density increases and voltage decreases.
Data Source
AI summary
A system receives a circuit description and measures of intrinsic delay, intrinsic delay variation, transition time and transition time variation for each stage and determines stage delay variation of each stage. The system receives a circuit description and derate factors and determines an intrinsic delay standard deviation and a correlation coefficient. The system determines a stage delay variation of each stage based on the determined factors. The system receives parameters describing an asymmetric distribution of delay values and generates a normal distribution of delay values. The system receives measures of nominal transition time at an output and input of a wire, and transition time variation at the input of the wire and determines a transition time variation at the output of the wire. The system receives measures of an Elmore delay and a nominal delay of the wire and determines a delay variation at the output of the wire.