Static Timing Data Integration for Functional Simulation Accuracy
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Solution Overview
Problem
Modern circuit designs face challenges in accurately simulating signal path delays due to the differences between functional simulation and static timing analysis, with functional simulation often providing overly optimistic results that do not reflect real-world operating conditions.
Innovation Solution
Integrating static timing data into the timing information used for functional simulation, specifically updating the Standard Delay Format (SDF) files with adjustments for clock uncertainty and clock arrival times to reflect worst-case scenarios, ensuring more accurate timing analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If functional simulation uses fixed delay information from SDF files representing extreme operating conditions, then the simulation can be performed efficiently with simplified timing parameters, but the timing information becomes overly optimistic and does not reflect variations in conditions during normal operation
Solution Approach 1:
The patent modifies the fixed delay parameters in SDF files by incorporating static timing analysis results. Specifically, it adjusts setup and hold timing parameters based on clock uncertainty and clock arrival time differences calculated through static timing analysis, transforming the static extreme-condition delays into dynamic adjusted parameters that reflect normal operating variations
Solution Approach 2:
The patent performs static timing analysis in advance to calculate clock uncertainty and clock arrival time differences before functional simulation. These pre-calculated values are then used to adjust the SDF timing parameters, allowing functional simulation to benefit from accurate timing information without performing complex dynamic timing analysis during the simulation process
2Measurement precision
If static timing analysis evaluates all possible paths with worst-case delay information, then the analysis provides accurate timing data reflecting normal operation variations, but it cannot account for dynamic behavior when inputs are applied
Solution Approach 1:
The patent divides the timing analysis into two separate phases: static timing analysis to evaluate all possible paths and calculate clock uncertainty/arrival time differences, and functional simulation to handle dynamic input behavior. The results from static analysis are used to adjust timing parameters in the functional simulation phase, allowing each method to operate in its optimal domain
Solution Approach 2:
The patent uses adjusted SDF timing parameters as an intermediary between static timing analysis and functional simulation. The static timing analysis results (clock uncertainty and arrival time differences) modify the SDF parameters, which then serve as the timing basis for functional simulation, bridging the gap between static worst-case analysis and dynamic functional verification
3Ease of operation
If functional simulation exercises only signal paths with applied input vectors, then the simulation can focus on specific test scenarios, but some signal paths may not be exercised and thus not evaluated
Solution Approach 1:
The patent makes the timing adjustment mechanism universal by applying static timing analysis results to all synchronous elements in the design, regardless of whether their paths are exercised by specific input vectors. This ensures that timing accuracy is improved across the entire design, not just for paths covered by functional simulation test cases
Data Source
AI summary
A method of generating timing information for a circuit design can include determining static timing data for the circuit design and identifying a source of timing information for use in functional simulation of the circuit design. The method also can include updating the source of timing information to include at least a portion of the static timing data.