Static Timing Analysis for Redundant Constraint Removal
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Solution Overview
Problem
Existing static timing analysis (STA) methods in integrated circuit (IC) design face challenges in identifying and removing redundant timing constraints, leading to erroneous chip performance, increased resource consumption, and prolonged development schedules.
Innovation Solution
A method and system for static timing analysis that involves obtaining a standard cell library file, performing topology mapping to identify target sequential cells, conducting a logic test to detect mutual non-controllable pin relationships, and removing redundant timing constraints to generate an optimized library file for improved chip design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional static timing analysis is performed using standard cell library files with timing constraints, then timing analysis can be conducted, but redundant timing constraints cause erroneous STA results and unnecessary chip design modifications
Solution Approach 1:
The patent applies preliminary action by performing topology mapping and logic testing on the standard cell library file before conducting static timing analysis. This pre-processing identifies and removes redundant timing constraints in advance, ensuring that the subsequent STA operates on cleaned data without encountering false constraints that would lead to erroneous results or unnecessary design modifications.
Solution Approach 2:
The system performs self-service by automatically detecting redundant timing constraints through topology mapping and logic testing, then removing them without requiring manual intervention. The standardized interface enables the system to self-correct the standard cell library file, eliminating the need for manual debugging and improving both reliability and productivity.
2Reliability
If manual or computer-aided debug methods are used to identify redundant timing constraints, then some redundant constraints can be found, but the process is time-consuming and difficult for standard cell libraries with thousands of circuits
Solution Approach 1:
The patent replaces manual mechanical debugging with an automated computer-based system that performs topology mapping and logic testing. This substitution transforms the debugging process from a time-consuming manual task into an efficient automated procedure that can rapidly analyze thousands of circuits in the standard cell library, significantly reducing debug time while maintaining or improving detection accuracy.
Solution Approach 2:
The system introduces an intermediary automated analysis layer between the standard cell library and the timing analysis process. This intermediary performs topology mapping to understand circuit structures and logic testing to identify redundant constraints, acting as a mediator that systematically processes the library file and eliminates redundant constraints before they affect STA results.
3Reliability
If chip design is modified to meet false timing constraints, then timing requirements are satisfied, but performance, power consumption and area decrease
Solution Approach 1:
The patent applies preliminary action by removing redundant timing constraints from the standard cell library file before conducting static timing analysis. This pre-cleaning of the constraint set ensures that the STA process identifies only genuine timing issues, preventing false positives that would otherwise trigger unnecessary design modifications and subsequent performance degradation.
Data Source
AI summary
A static timing analysis method and a static timing analysis system are provided. The static timing analysis methods includes: obtaining a standard cell library file for describing a plurality of standard cells; performing topology mapping on the standard cell library file to find out a target sequential cell from the standard cells, in which the sequential cell includes a logic gate, a selection circuit and a register circuit; executing a logic test process to find out a pin combination that has a mutual non-controllable relationship, and removing timing constraints related to the pin combination that are taken as redundant timing constraints from the standard cell library file, so as to generate an optimized standard library file; and perform a static timing analysis on a target circuit design according to the optimized standard cell library file.