Static Timing Slack Analysis for Transient Power Supply Variations
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Solution Overview
Problem
Existing integrated circuit (IC) design methods fail to accurately account for spatial and temporal variations in power supply voltage during static timing analysis, leading to inadequate consideration of transient power supply conditions.
Innovation Solution
A method and system for analyzing and modifying static timing slack in IC designs by constructing a timing model using upper and lower end voltage supplies, selecting a candidate timing path with minimum static timing slack, and determining transient static timing slack based on the transient power supply to adjust the timing of the IC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a one-for-all global supply voltage value is used to calculate delays for all elements, then the timing analysis is simple and fast, but it does not account for spatial and temporal variations in voltage, leading to inaccurate timing results
Solution Approach 1:
The patent segments the IC chip into multiple regions, each with its own power bus and voltage characteristics. Instead of using a single global voltage value, the timing analysis is performed separately for each region based on its specific voltage conditions, thereby capturing spatial variations while maintaining computational efficiency.
Solution Approach 2:
The patent performs preliminary power bus simulations to determine voltage values at different locations and times before conducting the timing analysis. These pre-computed voltage values are then used as inputs for the timing analysis, allowing the system to account for transient voltage variations without requiring complex real-time calculations during timing analysis.
2Measurement precision
If separate power bus analyses are performed for different switching objects to obtain transient voltage responses, then both spatial and temporal power supply variations are accounted for, but the run time cost becomes quite expensive
Solution Approach 1:
The patent applies local quality by performing detailed power bus analysis only for specific regions or paths that are identified as having significant timing impact, rather than uniformly analyzing all switching objects. This selective approach maintains accuracy for critical paths while reducing overall computational burden.
Solution Approach 2:
The patent performs power bus analysis for a subset of switching objects that are most critical to timing performance, rather than all switching objects. This partial action approach provides sufficient accuracy for timing-critical paths while significantly reducing the computational time required.
3Measurement precision
If voltage values based on leakage or average current demand are used to calculate element delays, then spatial variations are considered, but temporal variation in supply voltage is not accounted for
Solution Approach 1:
The patent transitions from static voltage values (based on average current) to dynamic voltage values that vary with time. By incorporating transient voltage responses from power bus simulations, the timing analysis can adapt to temporal voltage variations, making the delay calculations more accurate under dynamic operating conditions.
Data Source
AI summary
A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.