Statically Reconfigurable Dataflow Processor for N-Dimensional Affine Transform

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Solution Overview

Problem

Conventional CPUs and GPUs incur significant overhead due to dynamic reconfiguration and implicit instruction dependencies while performing affine transformations on images, which can hinder the efficiency of training neural networks and other applications requiring large numbers of image transformations.

Innovation Solution

A statically reconfigurable dataflow architecture processor (SRDAP) that maps an N-dimensional image affine transformation computation graph statically onto hardware, eliminating the need for dynamic instruction fetching and scheduling, and providing direct communication between dataflow pipelines to enhance throughput and reduce dependencies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional CPUs and GPUs are used to perform affine transformations, then the system can handle various computing tasks with flexibility, but significant overhead is incurred due to dynamic reconfiguration and implicit instruction dependencies

Engineering Contradiction:

Improvetask flexibilityVSAvoidtransformation efficiency

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The processor is divided into multiple independent dataflow pipelines (first pipeline, second pipeline, etc.) that can be independently configured and executed. Each pipeline handles specific portions of the affine transformation computation, allowing parallel processing while maintaining flexibility through selective activation of different pipeline configurations.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The processor implements static reconfiguration capability that allows the dataflow pipelines to be dynamically adjusted between different affine transformation operations. The configuration is established beforehand (statically) but can be changed between operations, providing adaptability without the overhead of dynamic instruction fetching during execution.

Inventive Principle:

Principle #15Dynamics

2Adaptability or versatility

If dynamic instruction fetching and scheduling is used in conventional processors, then the system can adapt to different operations, but overhead increases and throughput decreases

Engineering Contradiction:

Improveoperation adaptabilityVSAvoiddataflow throughput

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The dataflow pipelines are pre-configured with the necessary computation logic and data routing before execution begins. The affine transformation parameters and pipeline configurations are established in advance, eliminating the need for runtime instruction fetching and scheduling decisions, thus maximizing throughput while maintaining adaptability through pre-established configuration options.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent replaces the mechanical instruction fetching and scheduling mechanism with a dataflow-driven execution model. Instead of sequentially fetching and decoding instructions, the system uses data dependency-driven execution where computations are automatically performed when data becomes available, eliminating instruction overhead while maintaining operational flexibility.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Device complexity

If affine transformations are performed sequentially with implicit dependencies, then the system maintains simplicity in control logic, but execution time increases significantly

Engineering Contradiction:

Improvecontrol logic complexityVSAvoidtransformation execution time

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The affine transformation computation is segmented into multiple independent dataflow pipelines that can execute in parallel. Each pipeline handles specific computation stages or data portions, eliminating sequential dependencies and reducing execution time while maintaining relatively simple control logic within each pipeline.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The dataflow architecture enables continuous execution of affine transformations by eliminating idle wait states. Multiple pipelines operate continuously and independently, with data flowing through the system without interruption, maximizing resource utilization and reducing total execution time compared to sequential processing with implicit dependencies.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS20240232128A1Dataflow architecture processor statically reconfigurable to perform n-dimensional affine transformation in parallel manner by replicating copies of input image across scratchpad memory banks

Publication Date: 2024.07.11 SAMBANOVA SYSTEMS INC

AI summary

A statically reconfigurable dataflow architecture processor performs an N-dimensional affine transform specified by a matrix on an input image to produce an output image includes at least N+1 statically reconfigurable pattern compute units (PCUs) and pattern memory units (PMUs) each comprising a memory arranged as a vector of L banks. A first PMU writes a copy of the input image into each of the L banks. Each of N of the PCUs associated with the N dimensions is statically reconfigurable to apply a respective row of the transform matrix to N L-vectors of output pixel coordinates to generate a respective L-vector of input pixel coordinates. At least one of the PCUs flattens the N L-vectors of input pixel coordinates to calculate an L-vector of addresses. The first PMU uses the L addresses of the L-vector of addresses to read an L-vector of input pixels from the L banks in parallel.