Statistical Activity Analysis for Sequential Circuit Power Estimation
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Solution Overview
Problem
Current methods for circuit switching activity analysis are inefficient due to the lack of consideration for temporal and spatial correlations, leading to inaccurate power estimation and optimization in digital circuit designs, particularly in large-scale integrated circuits, where simulation-based methods require excessive time and resources.
Innovation Solution
The implementation of a temporal correlation network and an efficient encoding scheme to represent joint probabilities of signals, allowing for the analysis of temporal and spatial correlations, which reduces memory usage and improves accuracy by iteratively unrolling circuits within memory constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If simulation-based methods are used for circuit activity analysis, then accuracy of power estimation is improved, but analysis time and computational resources increase excessively
Solution Approach 1:
The patent segments the circuit into multiple sub-circuits or modules and performs activity analysis on each segment independently or hierarchically. This allows the overall analysis to be distributed and parallelized, reducing total analysis time while maintaining accuracy through localized statistical modeling of each segment's behavior.
Solution Approach 2:
The patent transforms the activity analysis problem from time-domain simulation to statistical parameter analysis in the frequency domain. By using spectral analysis and statistical moments (mean, variance, higher-order moments) to characterize signal behavior, the method achieves accurate power estimation without requiring lengthy time-domain simulations.
2Measurement precision
If temporal and spatial correlations are considered in activity analysis, then accuracy of power estimation is improved, but computational complexity and memory usage increase
Solution Approach 1:
The patent captures temporal and spatial correlations by analyzing statistical parameters (mean, variance, higher-order moments) and their relationships across different time instances and spatial locations. Instead of modeling full temporal sequences, the method uses parameter transformations that encode correlation information efficiently, reducing computational complexity while preserving accuracy.
Solution Approach 2:
The patent uses statistical parameter models that can be copied and applied to different circuit modules. Once the correlation structure is characterized for a module, the same parameter transformation approach can be replicated for other modules, avoiding redundant computation and reducing overall complexity through pattern reuse.
3Measurement precision
If full circuit unrolling is performed for activity analysis, then accuracy is improved, but memory usage becomes excessive
Solution Approach 1:
The patent segments the circuit and performs hierarchical analysis where only relevant portions of the circuit are fully unrolled and analyzed in detail. Other portions are analyzed using statistical parameter transformations that require minimal memory. This selective segmentation allows accurate analysis of critical paths while using compact representations for less critical areas.
Solution Approach 2:
The patent transforms the representation from full time-domain waveforms or detailed temporal sequences to compact statistical parameters (moments, spectral characteristics). This parameter transformation dramatically reduces memory requirements while preserving the essential information needed for accurate activity analysis and power estimation.
Data Source
AI summary
Techniques for statistical formal activity analysis with consideration of temporal and/or spatial correlations are described herein. According to one embodiment, a machine-implemented method for circuit analysis comprises unrolling a sequential circuit having a feedback loop into a plurality of unrolled circuits and introducing a spatial correlation via an encoding circuit coupled to the plurality of unrolled circuits for an activity analysis of the sequential circuit, the spatial correlation representing a dependency relationship between logic states of an input and logic states of other signals.