Statistical Circuit Simulation via Parallel Netlist Partitioning
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Solution Overview
Problem
Conventional circuit simulation methods, such as SPICE, face challenges in efficiently simulating large nanometer-scale integrated circuits due to increased matrix complexity, leading to high computational costs and impractical simulation times, especially when dealing with full chip designs.
Innovation Solution
The method involves partitioning circuits into groups based on statistical parameters and simulating these groups in parallel using a combination of graphics processing units (GPUs) and central processing units (CPUs), with shared memory for efficient model evaluations and load balancing to optimize simulation time and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional SPICE simulation methods are used for large nanometer-scale integrated circuits, then simulation accuracy is maintained, but simulation time and computational cost increase significantly
Solution Approach 1:
The patent partitions the large integrated circuit into multiple smaller sub-circuits or modules that can be simulated independently or in parallel. This segmentation reduces the computational burden on each simulation task while maintaining overall circuit accuracy through proper interconnection modeling.
Solution Approach 2:
The patent introduces parallel processing as an additional computational dimension by utilizing multiple processors or computing cores simultaneously. This transforms the traditional sequential simulation approach into a parallel architecture, dramatically reducing simulation time while preserving accuracy through coordinated multi-processing.
2Adaptability or versatility
If the circuit size is increased to accommodate more components, then circuit functionality is improved, but matrix complexity and computational difficulty increase
Solution Approach 1:
The patent divides large circuits with complex matrices into smaller manageable segments. Each segment generates a smaller matrix that is computationally tractable, while the overall system behavior is reconstructed by combining segment results with appropriate boundary conditions and interconnection models.
Solution Approach 2:
The patent applies simulation to essential circuit portions first, focusing computational resources on critical paths and functional blocks that most impact overall circuit behavior. Less critical areas are simulated with reduced detail or approximated, providing sufficient accuracy for design decisions without overwhelming computational complexity.
3Measurement precision
If detailed transistor-level simulation is performed, then nanometer effects are accurately analyzed, but simulation computational resources are excessively consumed
Solution Approach 1:
The patent applies detailed transistor-level simulation only to specific local regions or circuit blocks where nanometer effects are most significant, such as high-density logic areas or critical timing paths. Other regions are simulated with coarser models, optimizing the balance between capturing essential nanometer phenomena and conserving computational resources.
Solution Approach 2:
The patent performs comprehensive nanometer-level simulation only when necessary for specific design validation points, rather than uniformly across the entire circuit. This selective approach ensures accurate analysis of nanometer effects where they matter most while reducing overall computational resource consumption through targeted simulation depth.
Data Source
AI summary
Method and system are disclosed for statistical circuit simulation. In one embodiment, a computer implemented method for statistical circuit simulation includes providing descriptions of a circuit for simulation, wherein the descriptions include variations of statistical parameters of the circuit, partitioning the circuit into groups of netlists according to variations of statistical parameters of the circuit, simulating the groups of netlists using a plurality of processors in parallel to generate a plurality of output data files, and storing the plurality of output data files in a memory. The method of partitioning the circuit into groups of netlists includes forming the groups of netlists to be simulated in a single instruction multiple data environment, and forming the groups of netlists according to proximity of variations of statistical parameters of the circuit.