Statistical Interconnect Technology Profile for IC Design
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Solution Overview
Problem
Current IC design methods for post-layout simulation rely on extreme interconnect technology profile parameters, limiting design margin and causing overhead due to the need for extreme process conditions, which is not suitable for nano-scale integrated circuits.
Innovation Solution
A method for designing IC chips that involves extracting circuit parameters using a statistical interconnect technology profile file based on correlations of interconnect layer geometric parameter variations, allowing for more accurate simulation and detection of logic or timing errors, and generating a variation-aware ITP file using 3D simulations and Principal Component Analysis to reduce errors and increase design margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extreme interconnect technology profile parameters are used in post-layout simulation, then design coverage under extreme process conditions is improved, but design margin is reduced and overhead increases
Solution Approach 1:
The patent transforms the fixed extreme parameter approach into a statistical parameter model. Instead of using single extreme values, the invention implements a statistical ITP file that incorporates process variations through mean and standard deviation parameters. This allows simulation to cover extreme conditions implicitly through statistical distribution while avoiding the overhead of explicit extreme case analysis.
Solution Approach 2:
The patent creates a statistical representation (copy) of the actual process variations. The statistical ITP file serves as a simplified model that captures the essence of process variations without requiring physical extreme test cases. This statistical copy enables designers to assess variation impact efficiently while maintaining design margin.
2Productivity
If rule-based parasitic extraction is used with existing ITP, then extraction speed is maintained, but accuracy of parasitic RC variation assessment is reduced
Solution Approach 1:
The patent enhances the ITP parameters from simple fixed values to statistical distributions with mean and standard deviation. This parameter transformation enables the rule-based extractor to compute statistical parasitic variations directly during normal extraction flow, maintaining speed while improving accuracy of variation assessment.
Solution Approach 2:
The patent performs preliminary statistical analysis to generate the statistical ITP file before the actual parasitic extraction. This pre-computed statistical model contains all necessary information about process variations, allowing the extraction tool to efficiently compute parasitic variations without requiring additional extreme case simulations or measurements.
Data Source
AI summary
A method is provided for designing an IC chip. The method includes receiving data from a pre-layout design process for the IC chip, routing a plurality of interconnecting wires to connect various devices of the IC chip, and extracting various circuit parameters. The method also includes simulating the IC chip using the extracted various circuit parameters to detect logic or timing error in the IC chip. The extracting the various circuit parameters includes establishing a statistical interconnect technology profile (ITP) file containing at least interconnect parasitic parameters based on correlations of interconnect layer geometric parameter variations.