Statistical Place-and-Route for Timing Optimization
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Solution Overview
Problem
Existing semiconductor manufacturing design tools make pessimistic assumptions about on-chip variations, leading to suboptimal designs due to increased variations as feature size decreases, and fail to accurately account for layout context differences, resulting in penalized designs.
Innovation Solution
A statistical place-and-route technique that maintains local arrival and required time information, identifies critical paths, applies logical fixes based on adjusted slacks, and updates timing information to optimize circuit layouts, using statistical methods to model cell delays and slack values, thereby improving timing without overly pessimistic assumptions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pessimistic assumptions are used to account for on-chip variations, then timing reliability is improved, but design performance deteriorates due to penalized designs
Solution Approach 1:
The patent changes the parameter representation from deterministic worst-case values to statistical distributions (mean and standard deviation). By modeling cell delays, wire delays, and slack values as statistical parameters rather than fixed pessimistic values, the system achieves more accurate timing analysis that reflects actual manufacturing variations without unnecessarily penalizing design performance.
Solution Approach 2:
The patent replaces the traditional mechanical/deterministic timing analysis system with a statistical system. Instead of using fixed timing values and worst-case assumptions, the system employs statistical methods to model and analyze timing variations, substituting the old deterministic approach with a more sophisticated statistical framework that better represents real-world manufacturing variations.
2Quantity of substance
If feature size is decreased to improve chip density, then chip capacity is improved, but on-chip variations increase
Solution Approach 1:
The patent addresses increased manufacturing variations at smaller feature sizes by changing how timing parameters are represented. Instead of using fixed values that assume perfect manufacturing, the system uses statistical parameters (mean and standard deviation) to model the increased variations, allowing accurate timing analysis even when manufacturing precision deteriorates due to scaling.
3Reliability
If static timing analysis with pessimistic assumptions is used, then timing constraints are guaranteed to be met, but the resulting layout is suboptimal
Solution Approach 1:
The patent introduces dynamics into the timing analysis by using statistical distributions rather than static values. The timing analysis becomes dynamic in the sense that it accounts for the probability distribution of timing values rather than assuming a fixed worst-case scenario, allowing for more flexible and optimal layout decisions while still guaranteeing timing constraint satisfaction with high probability.
Solution Approach 2:
The patent employs feedback mechanisms where statistical timing information is propagated through the design and used to guide place-and-route decisions. The system continuously refines timing estimates based on statistical data from previous analysis stages, using this feedback to make informed decisions that optimize layout while ensuring timing constraints are met.
Data Source
AI summary
Place-and-route (P&R) includes maintaining a set of local arrival time information and local required time information associated with a circuit layout; determining a candidate fix on a critical path in the circuit layout; statistically determining, using one or more computer processors, a set of one or more adjusted local slacks associated with a region affected by the candidate fix; and in the event that the set of one or more adjusted local slacks indicates that the candidate fix results in a timing improvement, accepting the candidate fix.