Statistical Reference Voltage for Resistive Memory Sensing
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Solution Overview
Problem
Resistive nonvolatile memory (NVM) arrays, such as STT-MRAM, face challenges in accurately sensing stored data due to a small voltage range between low and high resistance states, leading to difficulties in designing reliable reference cells and increased chip area consumption with complex cell structures.
Innovation Solution
The implementation of a resistive NVM structure with two transistor-two variable resistor memory cells and one transistor-one variable resistor memory cells, where the first array generates a statistical reference voltage for the second array during read operations, reducing area consumption and eliminating the need for additional reference cells, and minimizing read errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex two transistor-two variable resistor memory cells are used, then sensing reliability is improved, but chip area consumption increases
Solution Approach 1:
The memory array is segmented into multiple blocks, where one block is dedicated as a reference block and other blocks are data blocks. This segmentation allows the reference voltage to be generated in-situ from the reference block, eliminating the need for separate reference cells and reducing overall chip area while maintaining sensing reliability through accurate statistical reference voltage generation.
Solution Approach 2:
The reference block serves multiple functions: it generates the statistical reference voltage for sensing operations, acts as part of the memory storage capacity, and provides process variation compensation. This multi-functionality eliminates the need for dedicated reference cells, thereby reducing chip area consumption while maintaining sensing reliability.
2Measurement precision
If separate reference cells are added to improve sensing accuracy, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The reference cell functionality is merged with the memory array structure itself by designating one or more memory blocks as reference blocks. This merging eliminates the need for separate, dedicated reference cells and their associated control circuitry, thereby reducing device complexity while maintaining sensing accuracy through statistical reference voltage generation from the reference block.
Solution Approach 2:
The memory array itself generates its own reference voltage through the reference block, which contains multiple variable resistors that produce a statistical reference voltage representing the mean resistance value. This self-service mechanism eliminates the need for external or separate reference cell circuits, reducing device complexity while maintaining sensing precision.
3Reliability
If more reference cells are added to minimize read errors, then reliability is improved, but manufacturing cost increases
Solution Approach 1:
The memory array is segmented into reference blocks and data blocks, where the reference blocks are used to generate statistical reference voltages. This segmentation allows the system to achieve high read accuracy through process variation compensation without adding dedicated reference cells, thereby reducing manufacturing complexity and cost while maintaining reliability.
Solution Approach 2:
The system changes from using fixed reference cell voltages to using statistical reference voltages generated by ensembles of variable resistors in reference blocks. This parameter change enables the system to compensate for process variations and minimize read errors without adding more reference cells, thereby reducing manufacturing cost while improving read accuracy.
Data Source
AI summary
A memory structure includes a first memory array with two transistor-two variable resistor memory cells and a second memory array with one transistor-one variable resistor memory cells, which are each selectively operable in read, write and standby modes. The first memory array and the second memory array are interleaved so that, when the second memory operates in the read mode, the first memory array automatically and concurrently operates in a reference mode. A method of operating the memory structure includes, when the second memory array operates in the read mode, automatically and concurrently operating the first memory array in the reference mode so that the first memory array generates and outputs a statistical reference voltage, which is between the low and high voltages of a nominal memory cell within the second memory array and which is employed by the second memory array to sense a stored data value.