Statistical Static Timing Analysis Corner Selection
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Solution Overview
Problem
Current techniques for selecting timing corners in integrated circuit design are inefficient and inaccurate, leading to long turn-around times and mis-correlation between non-signoff and signoff timing environments, and do not effectively model the actual hardware response.
Innovation Solution
A computer-implemented method and system for statistical static timing analysis that performs an initial analysis to create a parameterized model using multiple timing corners, determines the worst timing corner for each path, and enables subsequent analysis to optimize IC design by focusing on critical timing corners, thereby improving accuracy and reducing processing time and memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional static timing analysis is used with multiple timing corners to ensure accurate modeling of hardware response, then measurement precision is improved, but processing time and computational resources increase significantly
Solution Approach 1:
The patent segments the timing analysis process into two distinct phases: an initial comprehensive statistical static timing analysis that creates a parameterized model using multiple timing corners, and a subsequent focused analysis that uses only the identified worst timing corners. This segmentation allows the computationally intensive multi-corner analysis to be performed once, while subsequent iterations use only the critical corners, thereby reducing processing time without sacrificing accuracy.
Solution Approach 2:
The patent performs a preliminary statistical static timing analysis using multiple timing corners to create a parameterized model and identify the worst timing corners before conducting the main timing optimization. This preliminary action captures the essential timing characteristics and variability, allowing subsequent analyses to focus only on the critical worst corners, thus avoiding repeated full multi-corner analyses and reducing overall processing time.
2Manufacturing precision
If comprehensive multi-corner timing analysis is performed to accurately model hardware response, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts the worst timing corners from the comprehensive set of timing corners through statistical analysis of the parameterized model. By identifying and extracting only the critical worst corners that dominate timing failures, the system reduces the complexity of subsequent analyses while maintaining manufacturing precision. The extraction process filters out non-critical corners that do not significantly impact timing performance.
Solution Approach 2:
The patent changes the parameter set used in timing analysis by transitioning from a comprehensive set of multiple timing corners to a reduced set of identified worst timing corners. This parameter change is based on statistical analysis that determines which corners have the most significant impact on timing failures. The parameterized model allows dynamic adjustment of timing corner parameters based on actual circuit behavior and variability characteristics.
3Ease of operation
If traditional timing analysis methods are used without statistical modeling, then ease of operation is maintained, but reliability of timing predictions decreases
Solution Approach 1:
The patent introduces a parameterized model as an intermediary between the physical circuit and the timing analysis process. This model incorporates statistical variability parameters that capture manufacturing variations and environmental effects without requiring complex physical modeling. The parameterized model serves as a mediator that translates physical variability into timing predictions, maintaining ease of operation while significantly improving reliability of timing predictions.
Solution Approach 2:
The patent transforms the timing analysis from a deterministic approach to a statistical approach by changing the parameters used in the analysis. Instead of using fixed timing values, the system uses statistical parameters that model variability in process, voltage, and temperature. This parameter change enables the analysis to account for real-world variations while maintaining a manageable level of operational complexity through automated statistical methods.
Data Source
AI summary
Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In one example according to aspects of the present disclosure, a computer-implemented method is provided. The method comprises performing an initial statistical static timing analysis of the integrated circuit to create a parameterized model of the integrated circuit for a plurality of paths using a plurality of timing corners to calculate a timing value for each of the plurality of paths, each of the plurality of timing corners representing a set of timing performance parameters. The method further comprises determining at least one worst timing corner from the parameterized model for each of the plurality of paths based on the initial statistical static timing analysis and calculated timing value for each of the plurality of paths. The method also comprises performing a subsequent analysis of the integrated circuit using the at least one worst timing corner.