Order-Independent Statistical Timing Analysis for VLSI Circuits
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Solution Overview
Problem
Statistical Static Timing Analysis (SSTA) tools face challenges in accurately computing N-way maximum/minimum operations due to dependency on the order of pair-wise operations, leading to inaccuracy and inconsistency in timing analysis results for VLSI circuits with varying manufacturing and environmental sources of variation.
Innovation Solution
The method involves quantizing sources of variation using minimum distortion techniques, performing discrete maximum/minimum operations on quantized values, and de-quantizing results to maintain accuracy and consistency, allowing for order-independent N-way statistical maximum/minimum calculations with reduced computational complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If successive 2-way maximum/minimum operations are applied to compute N-way statistical maximum/minimum, then the operation can be performed using known 2-way methods, but the result becomes dependent on the order of pairings and accuracy becomes order-dependent
Solution Approach 1:
The patent segments the N-way statistical maximum/minimum operation into two independent parts: (1) statistical maximum/minimum of random variables, and (2) maximum/minimum of canonical form coefficients. This segmentation allows the operations to be performed independently and combines their results, eliminating order-dependency while maintaining computational efficiency.
Solution Approach 2:
The patent introduces an intermediary representation using quantized discrete values and canonical form coefficients as mediators between the input timing distributions and the final N-way maximum/minimum result. This intermediary structure enables order-independent computation by transforming the problem into a domain where the operations commute.
2Measurement precision
If order-independent N-way maximum/minimum operation is implemented, then accuracy and consistency are improved, but computational complexity increases
Solution Approach 1:
The patent changes the parameters of the timing distributions by quantizing them into discrete levels with associated probabilities, and representing the result in canonical form with new coefficients. This parameter transformation enables order-independent computation while controlling complexity through the quantization level and canonical form representation.
3Measurement precision
If quantization and de-quantization are applied to maintain accuracy, then order-independence is achieved, but additional computational steps are required
Solution Approach 1:
The patent applies preliminary quantization to the input timing distributions before performing the N-way maximum/minimum operation. This preliminary action transforms the continuous distributions into discrete representations that enable order-independent computation. The de-quantization step reconstructs the continuous canonical form result, maintaining accuracy while the structured approach controls the additional computational overhead.
Data Source
AI summary
A method and system to improve the performance of an integrated circuit (IC) chip by removing timing violations detected by performing a statistical timing analysis, given distributions of process and environmental sources of variation. The distributions are quantized using a minimum distortion criterion into discrete values. For each timing node of the IC circuit, a discrete minimum and maximum operation is performed on the timing parameters using a subset of combinations of the discrete values. The results of the discrete minimum and maximum operation are then de-quantized and propagated to a subsequent timing node and edge thereof. The process continues until one or more primary inputs and outputs of the IC chip are reached. The design of the IC chip is modified by removing all the timing violations identified.