Statistical Circuit Timing Analysis Using Generated PVT Corners

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Solution Overview

Problem

Existing circuit design analysis techniques face limitations in predicting failures due to design or manufacturing defects, particularly in very-large-scale integration circuits, as they often rely on deterministic timing analysis that assumes fixed values, leading to over-margining and potential hardware failures.

Innovation Solution

Generating additional PVT points using existing or known PVT points by pre-characterizing relationships between them, allowing for full parameterization and multi-dimensional statistical timing analysis without over-margining, thereby accounting for variability in process, voltage, and temperature.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If deterministic timing analysis is used, then analysis simplicity is maintained, but prediction accuracy deteriorates due to over-margining

Engineering Contradiction:
Improveanalysis simplicityVSAvoidprediction accuracy
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent transforms deterministic timing analysis into statistical timing analysis by changing the parameter representation from fixed values to probability distributions. This involves modeling timing parameters as random variables with specific distributions (e.g., normal, log-normal) rather than using single deterministic values, thereby capturing variability in process, voltage, and temperature effects without sacrificing computational feasibility.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent extends timing analysis from a single-point determination to a multi-dimensional statistical space by incorporating multiple standard deviation points (e.g., μ-3σ, μ-2σ, μ-1σ, μ, μ+1σ, μ+2σ, μ+3σ). This dimensional expansion allows the analysis to capture the full distribution of possible timing outcomes rather than relying on a single worst-case or nominal value.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If statistical timing analysis with multiple PVT points is performed, then prediction accuracy is improved, but computational complexity increases

Engineering Contradiction:
Improveprediction accuracyVSAvoidcomputational complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the statistical timing analysis into independent dimensional components, analyzing process, voltage, and temperature variations separately along each dimension before combining results through root-sum-square calculations. This segmentation allows complex multi-dimensional statistical analysis to be broken down into manageable one-dimensional analyses that can be performed systematically and combined efficiently.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs timing analysis at multiple discrete PVT corner points (e.g., μ-3σ to μ+3σ) which represents excessive sampling compared to a single deterministic analysis. By evaluating timing at these discrete statistical points and combining results through root-sum-square, the method achieves accurate statistical timing prediction without requiring exhaustive simulation of all possible continuous parameter combinations.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20260057160A1Generating parameters for statistical timing analysis of a circuit
Publication Date: 2026.02.26 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US20260057160A1 patent drawing
  • US20260057160A1 patent drawing
  • US20260057160A1 patent drawing

AI summary

Examples described herein provide a computer-implemented method that includes receiving a circuit design and a set of known process, voltage, and temperature (PVT) points for components of the circuit design. The method further includes determining parameter ratios for the set of known PVT points. The method further includes performing a statistical static timing analysis on the circuit design using the set of known PVT points and at least one additional PVT point generated during the statistical static timing analysis. The method further includes performing projections and root sum squaring for possible corners in a parameter space based on a canonical model generated during performing the statistical static timing analysis.