Statistical Static Timing Analysis for Pin Criticality Under Process Variations

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Integrated circuit design complexity due to process variations leads to challenges in accurately analyzing and optimizing timing parameters, as existing static timing analysis tools rely on nominal or worst-case values, which do not reflect actual semiconductor delays.

Innovation Solution

A system and method for computing timing pin criticalities using statistical static timing analysis, which calculates actual and required arrival times, computes slacks, and determines pin criticalities to identify and optimize timing issues in integrated circuit designs under process variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If static timing analysis uses nominal or worst case timing values, then the analysis is simple and fast, but the accuracy of timing prediction is poor due to not reflecting actual semiconductor delays

Engineering Contradiction:
Improvetiming prediction accuracyVSAvoidanalysis complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent transforms fixed nominal or worst-case timing values into probabilistic delay values by introducing statistical parameters (mean and standard deviation) to model process variations. This allows the timing analysis to reflect actual semiconductor delays while maintaining computational tractability through efficient statistical propagation algorithms.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent creates a statistical timing model that copies the circuit structure but replaces deterministic delay values with probability distributions. This statistical copy enables accurate timing prediction under process variations without requiring complex Monte Carlo simulations, thus improving accuracy while controlling analysis complexity.

Inventive Principle:
Principle #26Copying

2Measurement precision

If statistical static timing analysis is implemented to account for process variations, then timing prediction accuracy improves, but computational complexity and analysis time increase

Engineering Contradiction:
Improvetiming prediction accuracyVSAvoidanalysis time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent segments the timing analysis into two distinct phases: a forward pass to compute actual arrival times and their statistical moments, and a backward pass to compute required arrival times and criticality metrics. This segmentation enables efficient computation by avoiding full Monte Carlo simulations while maintaining statistical accuracy, thus reducing analysis time.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary computation of statistical moments (mean and standard deviation) of delay values before conducting the main timing analysis. By pre-calculating these statistical parameters and propagating them through the circuit, the method avoids repeated complex computations during the analysis, significantly reducing overall analysis time while maintaining accuracy.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If pin criticalities are computed under process variations, then optimization accuracy improves, but the computational resources required increase

Engineering Contradiction:
Improveoptimization accuracyVSAvoidcomputational resource requirements
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent enables the timing analysis system to self-determine pin criticalities by automatically propagating statistical moments through the circuit and computing criticality metrics without requiring external Monte Carlo simulations. The forward-backward pass algorithm self-sufficiently provides both timing analysis and criticality computation, reducing computational resource requirements while maintaining optimization accuracy.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8151229B1System and method of computing pin criticalities under process variations for timing analysis and optimization
Publication Date: 2012.04.03 CADENCE DESIGN SYST INC
  • US8151229B1 patent drawing
  • US8151229B1 patent drawing
  • US8151229B1 patent drawing

AI summary

A system and method for determining the criticality of each timing pin in a circuit design are disclosed. The criticality of a timing pin is the probability that the timing pin is on the path with the worst slack in the circuit design. According to the methodology, the slack for each timing pin is calculated, wherein each slack is a function of a process random variable. Then, the criticality of each timing pin is determined as the probability of the timing pin having the minimum slack among the slacks in an independent critical set of timing pins. The criticality of each timing pin may then be normalized. By determining the criticalities of the timing pins in a circuit design, a circuit design system may be able to more easily identify portions of the circuit design that need modification for timing and other purposes.