Statistical Static Timing Analysis Using Skewness
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Solution Overview
Problem
Existing electronic design automation (EDA) timing analysis methods are resource-intensive and often result in over-design due to the consideration of extreme on-chip variations, especially in asymmetrical distributions, leading to inefficient processing and potential inaccuracies in circuit design verification.
Innovation Solution
The use of skewness values to describe the asymmetry of on-chip variation probability distributions, allowing for the generation of statistical data structures that simplify timing analysis while maintaining accuracy, by modeling on-chip variation using sets of statistical values such as skew-normal, log-normal, or chi-squared distributions, which can be propagated through circuit designs to inform timing analysis operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional timing analysis methods consider extreme on-chip variations, then timing accuracy is improved, but processing resources are excessively consumed
Solution Approach 1:
The patent transforms the timing analysis approach by changing from considering extreme variations to using statistical parameters (mean, standard deviation, skewness) of on-chip variations. This parameter transformation enables accurate timing prediction while reducing computational complexity and resource consumption.
Solution Approach 2:
The patent replaces the traditional mechanical/extreme-based timing analysis method with a statistical modeling approach. By substituting extreme variation consideration with statistical distribution modeling (including skewness), the system achieves comparable accuracy with significantly reduced processing resources.
2Reliability
If traditional timing analysis methods consider extreme on-chip variations, then timing coverage is improved, but design efficiency deteriorates
Solution Approach 1:
The patent changes the approach from extreme-based timing coverage to statistical parameter-based analysis. By using mean, standard deviation, and skewness parameters to characterize on-chip variations, the method maintains comprehensive timing coverage while dramatically improving design efficiency and reducing turnaround time.
Solution Approach 2:
The patent creates statistical models (probability distribution functions) that copy and represent the complex behavior of on-chip variations. These statistical models serve as simplified representations that capture essential timing characteristics without requiring exhaustive extreme case analysis.
3Measurement precision
If asymmetrical on-chip variations are analyzed using traditional methods, then analysis accuracy is improved, but over-design occurs
Solution Approach 1:
The patent explicitly addresses asymmetrical on-chip variations by incorporating skewness as a statistical parameter in the timing analysis model. By recognizing and modeling the asymmetrical nature of variations rather than assuming symmetry, the method achieves accurate analysis without leading to over-design, as the statistical model precisely characterizes the actual variation distribution.
Solution Approach 2:
The patent introduces skewness as an additional parameter to characterize asymmetrical variations. This parameter change enables the model to accurately represent asymmetrical on-chip variations, preventing both over-design and under-design by matching the statistical model to the actual variation characteristics.
Data Source
AI summary
Electronic design automation systems, methods, and media are presented for characterizing on-chip variation of circuit elements in a circuit design using statistical values including skew, and for performing statistical static timing analysis using these statistical values. One embodiment models delay characteristics under certain operating conditions for circuit elements with asymmetric (e.g., non-Gaussian) probability density functions using normalized skewness. The modeled delay can then be used to perform various timing analysis operations.