Statistical Timing Verification for Semiconductor IC Clock Skew
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Solution Overview
Problem
Conventional timing verification methods for semiconductor integrated circuits face challenges in accurately evaluating variations in clock skew and signal path delay due to manufacturing variations, leading to unreliable timing verification results.
Innovation Solution
A method that statistically calculates clock skews and signal path delays, extracting partial circuits driven by clock signal pairs, and uses statistical timing characteristics to perform timing verification, considering factors like manufacture variations, voltage variations, and temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional timing verification methods are used, then timing verification can be performed, but the reliability of verification results is low due to inaccurate evaluation of variations in clock skew and signal path delay
Solution Approach 1:
The patent applies parameter changes by transitioning from deterministic timing verification to statistical timing verification. It introduces statistical parameters (mean and standard deviation) for clock skew and signal path delay, allowing the verification process to account for manufacturing variations, voltage variations, and temperature variations. This enables more accurate evaluation of timing characteristics under varying conditions, thereby improving both reliability and measurement precision.
Solution Approach 2:
The patent implements feedback by using the calculated statistical timing characteristics (mean and standard deviation of clock skew and signal path delay) to adjust and refine the timing verification process. The verification results feed back into the design process, allowing designers to iteratively improve circuit timing margins and account for real-world variations, thus enhancing the reliability of verification results.
2Measurement precision
If statistical calculation of clock skew and signal path delay is performed to improve verification accuracy, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the complex timing verification process into distinct stages: (1) statistical calculation of clock skew, (2) statistical calculation of signal path delay, (3) extraction of partial circuits driven by clock signal pairs, and (4) timing verification using statistical timing characteristics. This segmentation makes the complex statistical verification process more manageable and implementable while maintaining high measurement precision.
Data Source
AI summary
Initially, non-uniformity of statistical skews between a plurality of clock output terminal pairs is calculated. Next, a partial circuit driven by a clock output terminal pair having each skew distribution is extracted from an integrated circuit. Next, a second statistical timing characteristic which is a maximum value in the partial circuit is obtained from a first statistical timing characteristic of signal paths included in the extracted partial circuit. Next, timing verification for the integrated circuit is performed using the second statistical timing characteristics corresponding to the respective statistical clock skews.