Nonvolatile Status Register Write Sequencing for Erase-Life Extension
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Solution Overview
Problem
Nonvolatile status registers in memory chips experience reliability issues due to the upper limit of life after numerous erasing operations, as erasing operations are typically performed before writing, leading to reduced durability.
Innovation Solution
A memory chip design with a nonvolatile status register and control circuit that controls writing operations to exceed the number of erasing operations by performing writing multiple times before each erasing operation, distributing writing operations across groups of registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If erasing operations are performed before writing operations in general schemes, then the storage units can be prepared for new data, but the nonvolatile status registers reach an upper limit of life after more than hundreds of thousands of times erasing operations
Solution Approach 1:
The patent inverts the conventional operation sequence by performing writing operations before erasing operations on the nonvolatile status register. Specifically, the status register performs writing operations multiple times (e.g., 6 times) before a single erasing operation, reversing the traditional 'erase-then-write' sequence to 'write-then-erase'. This inversion reduces the frequency of erasing operations, thereby extending the lifespan and improving the reliability of the nonvolatile status register while maintaining proper operational readiness.
2Reliability
If multiple writing operations are performed before each erasing operation on the nonvolatile status register, then the equivalent erasing life is extended, but the control circuit complexity increases
Solution Approach 1:
The control circuit implements preliminary action by pre-managing the operation sequencing logic that performs multiple writing operations before triggering an erasing operation. The control circuit includes operation sequence management logic that tracks and controls the number of writing operations (e.g., counting to 6 writes) before initiating an erase cycle. This preliminary structuring of operation sequences extends the equivalent erasing life of the status register while keeping the control circuit complexity manageable through systematic sequencing rather than complex real-time control.
Data Source
AI summary
The present application discloses a memory chip. The memory chip includes a nonvolatile status register and a control circuit. The nonvolatile status register includes a plurality of groups of registers, each group of the registers includes a flag register and at least one data register, the control circuit is connected to the nonvolatile status register, and is configured to control writing times of the nonvolatile status register being greater than erasing times of the nonvolatile status register.