STC Clock Recovery Using Fractional Division for Multi-Format Sync
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Solution Overview
Problem
Existing audio and video decoding systems face challenges in generating multiple timing signals with varying frequencies using a single phase locked loop (PLL), particularly when dealing with different encoding schemes, which can lead to synchronization issues and increased manufacturing costs due to the need for multiple PLLs.
Innovation Solution
A system time clock recovery apparatus that includes a phase lock loop (PLL) and a fractional divider, which adjusts the STC frequency to generate a modified signal for the STC counter, allowing a single PLL to produce multiple timing signals, including audio clocks, thereby accommodating various encoding schemes without requiring additional PLLs on-chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple PLLs are used to generate different timing frequencies, then the system can accommodate different encoding schemes, but manufacturing costs increase and on-chip silicon area decreases
Solution Approach 1:
The patent implements a universal timing signal generation system where a single PLL can generate multiple timing frequencies (27 MHz and 54 MHz) through a frequency divider that can operate in different modes. This multi-functional approach allows the same hardware to accommodate both base extension and non-base extension encoding schemes without requiring separate PLL circuits, thereby reducing manufacturing costs while maintaining encoding scheme compatibility.
Solution Approach 2:
The patent combines the functions of multiple PLLs into a single PLL by introducing a frequency divider that can selectively divide the PLL output by different factors (1 or 2) to generate the required timing frequencies. This merging of functions reduces the number of separate components needed, decreasing on-chip silicon area and manufacturing complexity while preserving the ability to handle different encoding schemes.
2Adaptability or versatility
If multiple PLLs are used to generate different timing frequencies, then the system can accommodate different encoding schemes, but the on-chip silicon area decreases
Solution Approach 1:
The patent merges the functionality of multiple PLL circuits into a single PLL by adding a frequency divider component. This single integrated solution occupies less silicon area than multiple separate PLLs while providing the same adaptability to different encoding schemes through selective frequency division ratios.
Solution Approach 2:
The frequency divider is designed to be multi-functional, capable of operating in different division modes (division by 1 or 2) to support both 27 MHz and 54 MHz timing requirements. This universal component replaces multiple specialized PLL circuits, significantly reducing the required on-chip silicon area while maintaining full encoding scheme compatibility.
3Ease of manufacture
If a single PLL is used to generate both STC and audio clocks, then manufacturing costs are reduced, but the system cannot accommodate transport streams without STC base extension
Solution Approach 1:
The patent introduces dynamic configurability to the timing signal generation system through a frequency divider that can switch between different division ratios based on the encoding scheme being used. This dynamic adaptation allows a single PLL to serve multiple purposes: generating both STC and audio clocks for base extension schemes, and generating only audio clocks for non-base extension schemes, thereby achieving both cost reduction and encoding scheme compatibility.
Solution Approach 2:
The system changes the operational parameters of the frequency divider based on the detected encoding scheme. When base extension is present, the divider operates in one mode to generate both STC and audio clocks; when base extension is absent, the divider operates in a different mode to generate only audio clocks. This parameter adaptation enables a single PLL to accommodate multiple encoding schemes without requiring multiple PLL circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient synchronization of audio and video decoders across different encoding schemes, reducing manufacturing costs and eliminating the need for extra PLLs, while maintaining high audio-video synchronization performance.
Implementation Method 1
One common solution is to provide a phase locked loop (PLL) with a single voltage source to generate different frequencies such as audio frequencies for an audio decoder and STC clock frequency
Implementation Method 2
a fractional divider, which adjusts the STC frequency to generate a modified signal for the STC counter
Data Source
AI summary
Briefly, a system time clock (STC) recovery apparatus includes an STC counter that receives a program clock reference (PCR) signal. The STC recovery apparatus also includes a phase lock loop that generates an STC signal having an STC frequency and a fractional divider that generates a modified STC signal by adjusting the STC frequency of the STC signal such that the modified STC signal is provided to the STC counter. The STC clock recovery apparatus further includes a register, such as any suitable memory, which stores a target frequency value and a source frequency value. The target frequency value is the value of the target frequency for the modified STC signal and the source frequency value is the value of the frequency of the STC signal from the phase lock loop.