STI CMP Silicon Damage Reduction via Reverse Mask Transitioning
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Solution Overview
Problem
The shallow trench isolation (STI) CMP process during semiconductor fabrication often results in silicon damage and defects around the laser mark region due to incomplete removal of active-area oxide, leading to excessive pad nitride erosion and trench oxide loss.
Innovation Solution
A method is introduced where a reverse mask is used to expose the laser-marking region except for a transitioning region, allowing for complete removal of trench fill dielectric above the laser marking feature, and chemical mechanical polishing is conducted using the pad nitride layer as a polish stop, minimizing silicon damage by avoiding excessive over-polishing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional CMP process is used to remove trench fill dielectric, then complete removal of active-area oxide can be achieved, but silicon damage and defects occur around the laser mark region due to excessive over-polishing
Solution Approach 1:
The patent applies different CMP polishing conditions to different regions of the wafer. The laser mark region receives reduced polishing pressure or is excluded from over-polishing, while other regions maintain standard polishing parameters. This localized approach ensures complete trench fill removal in non-laser areas without causing silicon damage in the laser-marked area.
Solution Approach 2:
The patent performs preliminary selective removal of trench fill dielectric above the laser marking feature before the final CMP process. By pre-removing the dielectric in the laser mark region through selective etching or other non-CMP methods, the subsequent CMP process does not need to apply excessive polishing pressure to this area, thereby preventing silicon damage while maintaining complete removal in other regions.
2Manufacturing precision
If over-polishing is applied during STI CMP to ensure complete oxide removal, then manufacturing precision improves, but yield decreases due to induced silicon damage and defects
Solution Approach 1:
The patent implements region-specific polishing parameters where the laser mark region is identified and treated differently from the rest of the wafer. Polishing pressure, slurry flow, or platen speed are adjusted locally to prevent over-polishing in the laser-marked area, thereby maintaining high yield while ensuring complete oxide removal in critical non-laser regions.
Solution Approach 2:
The patent introduces an intermediary protective layer or mask over the laser mark region during CMP processing. This intermediary element prevents the polishing medium from directly acting on the silicon substrate in the laser-marked area, eliminating silicon damage while allowing complete oxide removal in exposed regions. The intermediary is then removed in a subsequent step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach widens the STI CMP process window and reduces silicon damage, ensuring complete removal of trench fill material without causing defects, thereby enhancing the yield and quality of semiconductor integrated circuits.
Implementation Method 1
A typical method of marking the lot identifier on a semiconductor wafer is by laser marking, where the laser locally melts the semiconductor in a pattern corresponding to the lot number and wafer number.
Implementation Method 2
chemical mechanical polishing is conducted using the pad nitride layer as a polish stop
Data Source
AI summary
A wafer has thereon a plurality of integrated circuit die areas, scribe line that surrounds each of the integrated circuit die areas, and a laser marking region having therein a laser marking feature. A pad layer is formed on the wafer. AA photoresist pattern is formed on the pad layer. The AA photoresist pattern includes trench openings that expose STI trench areas within the integrated circuit die areas and dummy openings that merely expose a transitioning region of the laser-marking region. The pad layer and the substrate are etched through the trench openings and dummy openings, to form STI trenches within the integrated circuit die areas and dummy trenches in the transitioning region. A trench fill dielectric is deposited over the wafer and fills the STI trenches and the dummy trenches. Using the pad nitride layer as a polish stop layer, chemical mechanical polishing the trench fill dielectric.