Stem Cell Layout Automation for Analog IC Design

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Solution Overview

Problem

The manual process of analog/mixed-signal layout in integrated circuit design is inefficient due to exponentially complex design rules, leading to increased engineering man-hours and time to delivery, with existing automation tools being fragile and costly to develop.

Innovation Solution

A methodology using stem cell libraries and digital P&R tools to automate the layout process, where stem cells have a core area for device elements and abutment boundaries for compliance with design rules, allowing for efficient placement and routing of analog/mixed-signal circuits alongside digital cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If manual layout process is used with pcells, then design flexibility and control are maintained, but engineering man-hours and time to delivery increase exponentially

Engineering Contradiction:
Improvelayout design speedVSAvoidtime to delivery
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The layout is segmented into standardized stem cell blocks that can be independently designed and reused. Each stem cell contains predefined device placements and routing patterns that comply with design rules, allowing rapid assembly of complex layouts from modular components rather than manual placement of individual polygons

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Stem cells are pre-designed with all design rule constraints already satisfied. The abutment boundaries and internal structures are prepared in advance to ensure compliance with complex design rules at recent technology nodes, eliminating the need for manual verification and adjustment during the layout process

Inventive Principle:
Principle #10Preliminary action

2Extent of automation

If existing automation tools are used, then layout automation is achieved, but the tools are fragile and costly to develop

Engineering Contradiction:
Improvelayout automation levelVSAvoidtool stability
Core Design Contradiction:
Extent of automationVSReliability

Solution Approach 1:

Instead of developing fragile custom automation tools, the invention creates reusable stem cell templates that can be copied and instantiated multiple times. These templates encapsulate proven design patterns and compliance logic, providing reliable automation through standardized components rather than custom software

Inventive Principle:
Principle #26Copying

3Manufacturing precision

If design rules are made compliant manually, then design rule compliance is achieved, but engineering man-hours increase due to exponential complexity

Engineering Contradiction:
Improvedesign rule complianceVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The invention transforms the complex design rule compliance problem into a parameterization problem. Stem cells are defined with specific geometric parameters and abutment boundary conditions that automatically satisfy design rules. By changing and reusing these parameters, compliance is achieved without manually navigating exponential complexity

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10808333B2Method and apparatus for performing layout designs using stem cells
Publication Date: 2020.10.20 TOTIC TECH INC
  • US10808333B2 patent drawing
  • US10808333B2 patent drawing
  • US10808333B2 patent drawing

AI summary

A method and system for designing an integrated circuit layout are disclosed. In one embodiment, the method includes generating a stem cell library with stem cell layouts, wherein each stem cell layout includes an analog core area where a device element resides, and abutment boundaries on left, right, top, and bottom sides of the analog core area. The method also includes mapping device elements in a schematic netlist to the stem cell layouts in the stem cell library. In addition, the method includes placing and routing the mapped device elements to optimize a layout for the schematic netlist.