Stencil Processor Architecture for Flexible, Power-Efficient Image Processing

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Solution Overview

Problem

Existing image processing technologies face a trade-off between versatility in application software development and power efficiency, with general-purpose processors consuming excessive energy and custom-designed circuits lacking flexibility.

Innovation Solution

An image processing unit (IPU) with a network of stencil processor circuits and sheet generators, utilizing a two-dimensional shift register array to process multiple overlapping stencils efficiently, allowing for both versatile programming and reduced power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If general purpose processors are used for image processing, then application software development versatility is improved, but power consumption per unit of data increases

Engineering Contradiction:

Improveapplication software development versatilityVSAvoidpower consumption per unit of data

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The image processing task is segmented into multiple independent stencil operations that can be executed in parallel. Each stencil processor handles a specific region or aspect of image processing, allowing the system to maintain versatility through programmable stencils while reducing per-unit-power consumption through parallel execution and specialized hardware acceleration.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The stencil processor is designed as a universal computing element that can execute multiple different stencil patterns and image processing algorithms through programmable instructions. This multi-functionality provides application software development versatility while the underlying fixed-function hardware architecture maintains power efficiency compared to general-purpose processors.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Use of energy by moving object

If custom designed fixed function circuitry is used, then power consumption per unit of data is reduced, but the set of performable tasks becomes limited

Engineering Contradiction:

Improvepower consumption per unit of dataVSAvoidset of performable tasks

Core Design Contradiction:

Use of energy by moving objectVSAdaptability or versatility

Solution Approach 1:

The stencil processor incorporates dynamic reconfigurability through programmable stencil patterns and processing parameters. This allows the fixed-function hardware to adapt to different image processing tasks by changing operational parameters rather than requiring different hardware circuits, thus maintaining both power efficiency and task versatility.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system achieves task diversity by changing operational parameters such as stencil size, shape, and processing algorithms through software control. This parameter-based adaptability allows custom-designed circuitry to perform multiple different image processing functions without sacrificing power efficiency or requiring general-purpose processing capabilities.

Inventive Principle:

Principle #35Parameter changes

3Use of energy by moving object

If larger blocks of data are processed by custom circuits, then power efficiency improves, but programming flexibility is lost

Engineering Contradiction:

Improvepower efficiencyVSAvoidprogramming flexibility

Core Design Contradiction:

Use of energy by moving objectVSEase of operation

Solution Approach 1:

The system processes image data in two-dimensional array blocks rather than simple linear sequences, maintaining power efficiency through large-block processing while adding the dimension of spatial organization. This 2D data structure enables more flexible programming models that can express complex image processing operations without sacrificing the power benefits of batch processing.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentEP3852050B1Architecture for high performance, power efficient, programmable image processing

Publication Date: 2025.07.30 GOOGLE LLC

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AI summary

An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a network. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.