Stencil Processor Core Architecture for Image Data Energy Efficiency

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Solution Overview

Problem

Existing image processing technologies face challenges in achieving a balance between energy efficiency and versatility, with traditional processors either consuming high energy due to software execution on general-purpose processors or being limited in functionality due to fixed-function hardware.

Innovation Solution

The development of a stencil processor architecture that combines a two-dimensional shift register array with an execution lane array, allowing for efficient processing of image data through overlapping stencils and providing a versatile hardware platform for a wide range of programmable functions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If software programs execute on a general purpose processor, then application versatility is improved, but energy consumption per unit of data increases

Engineering Contradiction:

Improveapplication versatilityVSAvoidenergy consumption per unit of data

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The processor is divided into multiple execution lanes (e.g., 16 lanes) that can operate in parallel, each capable of independent instruction execution. This segmentation allows the system to handle diverse applications through software while achieving higher throughput and better energy efficiency by distributing work across multiple specialized execution units rather than using a single general-purpose core.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The processor implements dynamic configuration capabilities where execution lanes can be selectively enabled or disabled based on workload requirements. The system can adapt its operational mode between fully parallel execution for performance-critical tasks and reduced-mode operation for power-constrained scenarios, allowing optimization of the versatility-energy tradeoff in real-time.

Inventive Principle:

Principle #15Dynamics

2Use of energy by moving object

If fixed function hardwired circuitry is applied to larger blocks of data, then power consumption per unit of data is reduced, but the set of performable tasks becomes limited

Engineering Contradiction:

Improvepower consumption per unit of dataVSAvoidset of performable tasks

Core Design Contradiction:

Use of energy by moving objectVSAdaptability or versatility

Solution Approach 1:

Each execution lane is designed with universal functionality to execute a wide range of instructions including integer operations, floating-point operations, and memory access instructions. The execution lanes can be configured through software to perform different functions, combining the energy efficiency of hardware execution with the versatility of programmable control, thus achieving multi-functionality without sacrificing power efficiency.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If finer grained data structures are used with software execution, then application versatility is improved, but overhead increases resulting in larger energy consumption

Engineering Contradiction:

Improveapplication versatilityVSAvoidinstruction overhead

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The processor merges the advantages of software flexibility with hardware efficiency by combining programmable execution lanes with vectorized data processing. Multiple data elements are processed in parallel within each execution lane using vector instructions, reducing the instruction overhead per unit of data while maintaining the ability to handle fine-grained data structures through software-controlled memory access patterns.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentEP3286722B1Energy efficient processor core architecture for image processor

Publication Date: 2025.03.12 GOOGLE LLC

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AI summary

An apparatus is described. The apparatus includes a program controller to fetch and issue instructions. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.