Semiconductor Package Step-Cut Leadframe for Probe Resistance

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Solution Overview

Problem

Existing leadframe chip packages are susceptible to physical probing or hardware hacking due to exposed perimeter lands, which can compromise sensitive information stored in integrated circuits.

Innovation Solution

A semiconductor package design featuring lead terminals with exposed outer ends at a step cut in the molding compound, which are shaded and protected, reducing the vulnerability to physical probing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If lead terminals are exposed at the perimeter of the package, then electrical connection and soldering are facilitated, but the package becomes susceptible to physical probing and hardware hacking

Engineering Contradiction:
Improveease of solderingVSAvoidvulnerability to physical probing
Core Design Contradiction:
Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a step cut feature that creates a vertical dimension change in the molding compound. The lead terminals are exposed at this stepped region rather than at the perimeter, moving the exposure point from a two-dimensional perimeter to a three-dimensional stepped surface, thereby maintaining soldering access while reducing probing vulnerability

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The step cut in the molding compound acts as an intermediary structure that mediates between the need for lead terminal exposure and the need for security. It provides a controlled exposure point that facilitates soldering while the surrounding molding compound at the perimeter continues to provide protective shielding against physical probing

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If molding compound fully encapsulates lead terminals, then security against physical probing is improved, but accessibility for soldering and electrical connection is reduced

Engineering Contradiction:
Improveprotection from physical probingVSAvoidaccessibility for soldering
Core Design Contradiction:
Object-affected harmful factorsVSEase of operation

Solution Approach 1:

The patent segments the molding compound encapsulation by introducing a step cut that creates distinct regions: a lower region where lead terminals are exposed for soldering, and an upper region where molding compound provides protective encapsulation. This segmentation allows simultaneous achievement of both soldering accessibility and security protection

Inventive Principle:
Principle #1Segmentation

3Object-affected harmful factors

If package thickness is increased to provide better protection, then security is improved, but the package size and complexity increase

Engineering Contradiction:
Improvesecurity enhancementVSAvoidpackage structure complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

Rather than increasing package thickness uniformly in all directions, the patent introduces a step cut that creates a localized vertical dimension change. This allows security enhancement through increased molding compound coverage at critical areas while maintaining overall package compactness and avoiding uniform thickness increase that would add complexity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12205869B2Method for forming a semiconductor package
Publication Date: 2025.01.21 MEDIATEK INC
  • US12205869B2 patent drawing
  • US12205869B2 patent drawing
  • US12205869B2 patent drawing

AI summary

A semiconductor package includes a die attach pad; a plurality of lead terminals disposed around the die attach pad; a semiconductor die mounted on the die attach pad; a molding compound encapsulating the plurality of lead terminals, the semiconductor die, and the die attach pad; and a step cut sawn into the molding compound along a perimeter of a bottom surface of the semiconductor package. The step cut penetrates through an entire thickness of each of the plurality of lead terminals, whereby each of the plurality of lead terminals has at least an exposed outer end at the step cut.