Step Doped SSRW FET Channel Profile Formation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for forming super steep retrograde well (SSRW) field effect transistors (FETs) face challenges in achieving steep channel profiles due to high energy and high dosage implantations, which are difficult below 20 nanometers and result in dopant impurities and threshold voltage variations, especially in advanced technology nodes.
Innovation Solution
The method involves performing deep and shallow well implantations prior to growing carbon-doped silicon (Si:C), using lower energy implants and forming recesses by reactive ion etching or anisotropic wet etching, followed by epitaxial growth and thermal treatment to achieve a well-controlled step doped channel profile compatible with subsequent thermal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high energy and high dosage implantation is used to achieve desired dopant concentration, then the dopant concentration can be achieved 20 nm to 30 nm below the gate dielectric layer, but the method becomes difficult to apply for 20 nm and beyond fabrication technology and causes dopant impurities in the channel surface region
Solution Approach 1:
The implantation process is divided into multiple sequential implantation steps with different energies and dosages, rather than using a single high energy/high dosage implantation. This segmentation allows precise control of dopant concentration at different depths while avoiding the need for high energy implantation that is difficult to apply at 20 nm and below.
Solution Approach 2:
A preliminary low energy implantation is performed first to create a dopant profile without causing significant diffusion or impurity migration. Subsequent implantation steps then build upon this preliminary profile to achieve the final desired concentration distribution, avoiding the harmful effects of high energy implantation.
2Manufacturing precision
If high energy and high dosage implantation is performed, then the desired dopant concentration can be achieved, but dopant impurities migrate upwards during threshold adjust well implantation causing threshold voltage variation and degraded device performance
Solution Approach 1:
The deep well implantation is performed as a preliminary action before threshold adjust implantation. By establishing the deep dopant profile first with controlled low energy implantation, the subsequent threshold adjust implantation does not cause significant dopant migration from the deep well, thereby maintaining threshold voltage stability.
Solution Approach 2:
The implantation energy and dosage parameters are optimized and changed across multiple steps. Low energy and controlled dosage are used for deep well implantation to prevent dopant migration, while subsequent steps use adjusted parameters to fine-tune the profile, ensuring both concentration control and threshold voltage stability.
3Reliability
If blanket epitaxial Si:C is grown after STI formation and CMP, then a diffusion barrier can be formed, but step height difference between active regions and field oxide causes process issues during polysilicon gate electrode formation
Solution Approach 1:
Instead of blanket epitaxial growth, the Si:C diffusion barrier is grown selectively only in the active regions where it is needed. This local growth approach ensures that the diffusion barrier is formed precisely where required while maintaining a flat surface topology, eliminating step height differences that would cause gate height non-uniformity.
Solution Approach 2:
The Si:C diffusion barrier is grown as a preliminary step before polysilicon gate electrode formation. By establishing the barrier layer in advance with controlled thickness and selective growth, the subsequent gate formation process proceeds uniformly without encountering step height issues, ensuring both diffusion protection and gate uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of steep channel profiles with reduced impurities and threshold voltage variations, enhancing device performance and compatibility with advanced technology nodes like 32 nanometer nodes and beyond.
Implementation Method 1
performing a deep well implantation of a dopant into the silicon wafer between STI regions
Implementation Method 2
forming recesses by reactive ion etching or anisotropic wet etching
Implementation Method 3
forming carbon-doped silicon (Si:C) on the doped silicon wafer in the recess
Implementation Method 4
limited by the diffusion of p-type dopants during subsequent thermal processes
Data Source
AI summary
A methodology enabling the formation of steep channel profiles for devices, such as SSRW FETs, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing STI regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between STI regions; forming a recess in the doped silicon wafer between the STI regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming Si:C on the doped silicon wafer in the recess.