Step-Down Stencil for Ball Drop on Thin Wafers With Edge Support Ring

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The existing ball drop process for forming bumps on semiconductor wafers with edge support rings is ineffective due to the non-planar surface and the inability of traditional stencils to accurately place bumps on interconnect pads.

Innovation Solution

A specialized stencil design that includes a step-down portion to align openings with the interconnect pads within the edge support ring, ensuring precise placement of bumps on the conductive layer, even on non-planar surfaces.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a traditional flat stencil is used for ball drop process, then the stencil can be simple in structure, but the bumps cannot be accurately placed on interconnect pads due to non-planar surface caused by edge support ring

Engineering Contradiction:
Improvebump placement accuracyVSAvoidstencil structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The stencil transitions from a two-dimensional flat structure to a three-dimensional structure with a step-down portion that creates different height levels. This dimensional change allows the stencil to accommodate the non-planar surface created by the edge support ring while maintaining accurate bump placement on the interconnect pads.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The stencil is designed with different regions having different heights: a first portion at a higher level and a second portion (step-down portion) at a lower level. This local quality variation allows the stencil to make contact with both the edge support ring area and the recessed interconnect pad area, enabling precise bump placement only where needed.

Inventive Principle:
Principle #3Local quality

2Volume of moving object

If the wafer thickness is reduced to minimize package size, then the semiconductor device becomes more compact, but the wafer becomes susceptible to warpage without support

Engineering Contradiction:
Improvepackage sizeVSAvoidwafer warpage
Core Design Contradiction:
Volume of moving objectVSStability of the object's composition

Solution Approach 1:

The wafer structure is segmented into two functional regions: an edge support ring that maintains structural stability and prevents warpage, and a recessed interior region that allows for reduced overall thickness. This segmentation enables the wafer to be thin for compact packaging while maintaining rigidity through the peripheral support structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The edge support ring is formed in advance to counteract the warpage tendency of the thin wafer before the ball drop process. By pre-establishing this support structure, the wafer maintains planarity in the critical interior region where interconnect pads are located, enabling subsequent precise bump placement.

Inventive Principle:
Principle #9Preliminary anti-action

3Manufacturing precision

If the stencil openings are aligned with interconnect pads on non-planar surface, then accurate bump placement is achieved, but the stencil design becomes complex with step-down portions

Engineering Contradiction:
Improvebump placement accuracyVSAvoidstencil fabrication difficulty
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The stencil incorporates a step-down portion that creates a vertical dimension difference, allowing openings to be positioned at different heights. This enables accurate alignment with interconnect pads on the non-planar surface while maintaining a relatively simple fabrication process that can create controlled height variations.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250062263A1Semiconductor wafer and method of ball drop on thin wafer with edge support ring
Publication Date: 2025.02.20 SEMICON COMPONENTS IND LLC
  • US20250062263A1 patent drawing
  • US20250062263A1 patent drawing
  • US20250062263A1 patent drawing

AI summary

A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.